參數(shù)資料
型號(hào)： MCF5232
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Integrated Microprocessor Hardware Specification
中文描述： 集成的微處理器，硬件規(guī)格
文件頁(yè)數(shù)： 17/60頁(yè)
文件大?。?/td> 1462K
代理商： MCF5232
Design Recommendations
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Preliminary
Freescale Semiconductor
17
3.2.2
WAIT Mode
WAIT mode is intended to be used to stop only the CPU core and memory clocks until a wakeup event is
detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts,
which cause the CPU core to exit from WAIT mode.
3.2.3
DOZE Mode
DOZE mode affects the CPU core in the same manner as WAIT mode, but with a different code on the
CIM LPMD bits, which are monitored by the peripherals. Each peripheral defines individual operational
characteristics in DOZE mode. Peripherals which continue to run and have the capability of producing
interrupts may cause the CPU to exit the DOZE mode and return to the RUN mode. Peripherals which are
stopped will restart operation on exit from DOZE mode as defined for each peripheral.
3.2.4
STOP Mode
STOP mode affects the CPU core in the same manner as the WAIT and DOZE modes, but with a different
code on the CCM LPMD bits. In this mode, all clocks to the system are stopped and the peripherals cease
operation.
STOP mode must be entered in a controlled manner to ensure that any current operation is properly
terminated. When exiting STOP mode, most peripherals retain their pre-stop status and resume operation.
3.2.5
Peripheral Shut Down
Most peripherals may be disabled by software in order to cease internal clock generation and remain in a
static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description
for further details). A peripheral may be disabled at anytime and will remain disabled during any low
power mode of operation.
4
Design Recommendations
4.1
Layout
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF523
x
.
See application note AN1259 System Design and Layout Techniques for Noise Reduction in
processor-Based Systems.
Match the PC layout trace width and routing to match trace length to operating frequency and
board impedance. Add termination (series or therein) to the traces to dampen reflections.
Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do
cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6
mils trace and separation. Clocks get extra separation and more precise balancing.
相關(guān)PDF資料
PDF描述
MCF5249 CodeWarrior Development Studio for ColdFire㈢ Architectures
MCF5251_07 ColdFire㈢ Microprocessor Data Sheet
MCF5251 ColdFire Processor
MCF5253 ColdFire㈢ Microprocessor Data Sheet
MCF5270AB100 Integrated Microprocessor Hardware Specification
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