參數(shù)資料
型號: MCF5232
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Integrated Microprocessor Hardware Specification
中文描述: 集成的微處理器,硬件規(guī)格
文件頁數(shù): 38/60頁
文件大?。?/td> 1462K
代理商: MCF5232
MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3
Preliminary
Preliminary Electrical Characteristics
Freescale Semiconductor
38
6.4
Oscillator and PLLMRFM Electrical Characteristics
Table 29. HiP7 PLLMRFM Electrical Specifications
1
Load Capacitance
4
Low drive strength
High drive strength
C
L
25
50
pF
Core Operating Supply Current
5
Master Mode
I
DD
TBD
mA
Pad Operating Supply Current
Master Mode
Low Power Modes
OI
DD
TBD
TBD
mA
μ
A
DC Injection Current
3,
6, 7, 8
V
NEGCLAMP
=V
SS
– 0.3 V, V
POSCLAMP
= V
DD
+ 0.3
Single Pin Limit
Total processor Limit, Includes sum of all stressed pins
I
IC
–1.0
–10
1.0
10
mA
NOTES:
1
Refer to Table 29 for additional PLL specifications.
2
Refer to the MCF5235 signals section for pins having weak internal pull-up devices.
3
This parameter is characterized before qualification rather than 100% tested.
4
pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination. See High Speed Signal
Propagation: Advanced Black Magic by Howard W. Johnson for design guidelines.
5
Current measured at maximum system clock frequency, all modules active, and default drive strength with matching
load.
6
All functional non-supply pins are internally clamped to V
SS
and their respective V
DD
.
7
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
8
Power supply must maintain regulation within operating V
DD
range during instantaneous and operating maximum
current conditions. If positive injection current (V
in
> V
DD
) is greater than I
DD
, the injection current may flow out of V
DD
and could result in external power supply going out of regulation. Insure external V
DD
load will shunt current greater
than maximum injection current. This will be the greatest risk when the processor is not consuming power. Examples
are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at
power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
1
PLL Reference Frequency Range
Crystal reference
External reference
1:1 mode (NOTE: f
sys/2
= 2
×
f
ref_1:1
)
f
ref_crystal
f
ref_ext
f
ref_1:1
8
8
24
25
25
75
MHz
2
Core frequency
CLKOUT Frequency
2
External reference
On-Chip PLL Frequency
f
sys
f
sys/2
0
f
ref
÷
32
150
75
75
MHz
MHz
MHz
3
Loss of Reference Frequency
3, 5
f
LOR
100
1000
kHz
4
Self Clocked Mode Frequency
4, 5
f
SCM
TBD
TBD
MHz
Table 28. DC Electrical Specifications
1
Characteristic
Symbol
Min
Max
Unit
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