參數(shù)資料
型號： MC94MX21DVKN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 350 MHz, MICROPROCESSOR, PBGA289
封裝： 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289
文件頁數(shù)： 45/98頁
文件大?。?/td> 1326K
代理商： MC94MX21DVKN3R2
Signal Descriptions
MC94MX21 Technical Data, Rev. 1.
5
Freescale Semiconductor
5
The connections of the pins in Table 2 depends solely upon the user application, however there are a few
factory test signals that are not used in a normal application. Following is a list of these signals and how
they are to be terminated for proper operation of the i.MX21 processor:
CLKMODE[1:0]: To ensure proper operation, leave these signals as no connects.
OSC26M_TEST: To ensure proper operation, leave this signal as no connect.
EXT_48M: To ensure proper operation, connect this signal to ground.
EXT_266M: To ensure proper operation, connect this signal to ground.
TEST_WB[2:0]: These signals are also multiplexed with GPIO PORT E as well as alternate
keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed
function, then configure as GPIO input with pull up enabled, and leave as a no connect.
TEST_WB[4:3]: To ensure proper operation, leave these signals as no connects.
Table 2. i.MX21 Signal Descriptions
Signal Name
Function/Notes
External Bus/Chip Select (EIM)
A [25:0]
Address bus signals
D [31:0]
Data bus signals
EB0
MSB Byte Strobe—Active low external enable byte signal that controls D [31:24], shared with SDRAM
DQM0.
EB1
Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.
EB2
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2
and PCMCIA PC_REG.
EB3
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
OE
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.
CS [5:0]
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is
selected. DTACK is multiplexed with CS4.
ECB
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-
going burst sequence and initiate a new (long first access) burst sequence.
LBA
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
BCLK
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also
shared with the PCMCIA PC_WE.
DTACK
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
Bootstrap
BOOT [3:0]
System Boot Mode Select—The operational system boot mode upon system reset is determined by the
settings of these pins. To hardwire these inputs low, terminate with a 1 K
Ω resister to ground. For a logic
high, terminate with a 1 K
Ω resistor to VDDA. Do not change the state of these inputs after power-up.
Boot 3 should always be tied to logic low.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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