參數(shù)資料
型號(hào)： MC94MX21DVKN3R2
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 350 MHz, MICROPROCESSOR, PBGA289
封裝： 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289
文件頁(yè)數(shù)： 29/98頁(yè)
文件大?。?/td> 1326K
代理商： MC94MX21DVKN3R2
Specifications
MC94MX21 Technical Data, Rev. 1.
5
Freescale Semiconductor
35
3.12
Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/
SD module (inner system) and the application (user programming).
Figure 25. Chip-Select Read Cycle Timing Diagram
Table 25. SDHC Bus Timing Parameters
Ref
No.
Parameter
1.8 V
± 0.1 V
3.0 V
± 0.3 V
Unit
Min
Max
Min
Max
1
CLK frequency at Data transfer Mode (PP)1
—10/30 cards
1. CL ≤ 100 pF / 250 pF (10/30 cards)
025/5
0
25/5
MHz
2
CLK frequency at Identification Mode2
2. CL ≤ 250 pF (21 cards)
0
400
0
400
kHz
3a
Clock high time1
—10/30 cards
6/33
–
10/50
–
ns
3b
Clock low time1
—10/30 cards
15/75
–
10/50
–
ns
4a
Clock fall time1
—10/30 cards
–
10/50 (5.00)3
–
10/50
ns
4b
Clock rise time1
—10/30 cards
–
14/67 (6.67)3
–
10/50
ns
5a
Input hold time3
—10/30 cards
3. CL ≤ 25 pF (1 card)
5.7/5.7
–
5/5
–
ns
5b
Input setup time3
—10/30 cards
5.7/5.7
–
5/5
–
ns
6a
Output hold time3
—10/30 cards
5.7/5.7
–
5/5
–
ns
6b
Output setup time3
—10/30 cards
5.7/5.7
–
5/5
–
ns
7
Output delay time3
0
16
0
14
ns
Bus Clock
5b
6b
6a
7
5a
4a
3a
CMD_DAT Input
CMD_DAT Output
4b
3b
Valid Data
1
2
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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參數(shù)描述
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