參數(shù)資料
型號(hào)： MC94MX21DVKN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 350 MHz, MICROPROCESSOR, PBGA289
封裝： 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289
文件頁數(shù)： 19/98頁
文件大?。?/td> 1326K
代理商： MC94MX21DVKN3R2
MC94MX21 Technical Data, Rev. 1.
5
26
Freescale Semiconductor
Specifications
3.8.3.1
Memory Interface Master Mode Without WAIT Signal
The WAIT control bit (BMICTLR1[29]) is used in this mode. When this bit is cleared (default), the
BMI_WAIT signal is ignored and the CS cycle is terminated by Wait State (WS) control bits. Figure 11
shows the BMI timing when the WAIT bit is cleared.
Figure 11. Memory Interface Master Mode, BMI Read/Write to External Slave Device Timing without Wait
Signal (MMD_MODE_SEL=0, MASTER_MODE_SEL=1)
3.8.3.2
Memory Interface Master Mode with WAIT Signal
When the WAIT control bit is set, the BMI_WAIT signal is used and the CS cycle is terminated upon
sampling a logic high BMI_WAIT signal. Figure 12 shows the BMI write timing when the WAIT bit is set.
When the BMI_WRITE is asserted, the BMI will detect the BMI_WAIT signal on every falling edge of
the Int_Clk. When it detected the high level of the BMI_WAIT, the BMI_WRITE will be negated after
1+WS Int_Clk period. If the BMI_WAIT is always high or already high before BMI_WRITE is asserted,
this timing will same as without WAIT signal. So the BMI_WRITE will be asserted at least for 1+WS
Int_Clk period.
1+ws
BMI_READ
BMI_WRITE
Int_Clk
BMI_CLK/CS
BMI_READ_REQ
Int_write
BMI_D[15:0]
TxD1
TxD2
Last TxD
RxD1
RxD2
1+ws
DMA or CPU write data to TxFIFO
On the next Int_Clk BMI issues a write cycle
BMI_READ_REQ is still logic high, BMI issues next write cycle
A 1 is written to READ bit of control reg1
BMI write
Tdh
(reference only)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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