參數(shù)資料
型號： MC94MX21DVKN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 350 MHz, MICROPROCESSOR, PBGA289
封裝： 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289
文件頁數(shù)： 3/98頁
文件大?。?/td> 1326K
代理商： MC94MX21DVKN3R2
Signal Descriptions
MC94MX21 Technical Data, Rev. 1.
5
Freescale Semiconductor
11
USBH1_RXDP
USB Host1 Receive Data Plus input signal. This signal is multiplexed with UART4_RXD and
SLCDC1_DAT6. It also provides an alternative multiplex for UART4_RTS, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USBH1_RXDM
USB Host1 Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT5. It also provides
an alternative multiplex for UART4_CTS.
USBH1_TXDP
USB Host1 Transmit Data Plus output signal. This signal is multiplexed with UART4_CTS and
SLCDC1_DAT4. It also provides an alternative multiplex for UART4_RXD, where this signal is selectable
by programming the Function Multiplexing Control Register in the System Control chapter.
USBH1_TXDM
USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3.
USBH1_RXDAT
USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS.
USBH1_OE
USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2.
USBH1_FS
USB Host1 Full Speed output signal. Multiplexed with UART4_RTS and SLCDC1_DAT1 and
USBH1_RXDAT.
USBH_ON
USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0.
USBH2_RXDP
USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2.
USBH2_RXDM
USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2.
USBH2_TXDP
USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2.
USBH2_TXDM
USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2.
USBH2_OE
USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2.
USBH2_FS
USB Host2 Full Speed output signal. This signal is multiplexed with CSPI2_SS[0] of CSPI2.
USBG_SCL
USB OTG I2C Clock input/output signal. This signal is multiplexed with SLCDC1_DAT8.
USBG_SDA
USB OTG I2C Data input/output signal. This signal is multiplexed with SLCDC1_DAT7.
USBG_TXR_INT
USB OTG transceiver interrupt input. Multiplexed with USBG_FS.
Secure Digital Interface
SD1_CMD
SD Command bidirectional signal—If the system designer does not want to make use of the internal pull-
up, via the Pull-up enable register, a 4.7k–69k external pull-up resistor must be added. This signal is
multiplexed with CSPI3_MOSI.
SD1_CLK
SD Output Clock. This signal is multiplexed with CSPI3_SCLK.
SD1_D[3:0]
SD Data bidirectional signals—If the system designer does not want to make use of the internal pull-up,
via the Pull-up enable register, a 50k–69k external pull-up resistor must be added. SD1_D[3] is muxed
with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO.
SD2_CMD
SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1.
SD2_CLK
SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1.
SD2_D[3:0]
SD Data bidirectional signals. SD2_D[3:2] are multiplexed with SLCDC1_RS and SLCDC_D0 signals
from SLCDC1.
UARTs – IrDA/Auto-Bauding
UART1_RXD
Receive Data input signal
UART1_TXD
Transmit Data output signal
UART1_RTS
Request to Send input signal
UART1_CTS
Clear to Send output signal
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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MC94MX21DVKN3R2 制造商:Freescale Semiconductor 功能描述:32-bit Embedded Microprocessors
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