參數(shù)資料
型號： MC8640DHX1067NE
廠商： Freescale Semiconductor
文件頁數(shù)： 40/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標準包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.067GHz
電壓： 0.95V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
17
Input Clocks
4.2
Real Time Clock Timing
The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then
used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of
the RTC signal should be greater than 2
× the period of the MPX clock. That is, minimum clock high time
is 2
× tMPX, and minimum clock low time is 2 × tMPX. There is no minimum RTC frequency; RTC may be
grounded if not needed.
4.3
eTSEC Gigabit Reference Clock Timing
Table 10 provides the eTSEC gigabit reference clocks (EC1_GTX_CLK125 and EC2_GTX_CLK125) AC
timing specifications for the MPC8640.
NOTE
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
4.4
Platform Frequency Requirements for PCI-Express and Serial
RapidIO
The MPX platform clock frequency must be considered for proper operation of the high-speed PCI
Express and Serial RapidIO interfaces as described below.
For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:
527 MHz x (PCI-Express link width)
16 / (1 + cfg_plat_freq)
Table 10. EC
n_GTX_CLK125 AC Timing Specifications
Parameter
Symbol
Min
Typical
Max
Unit
Notes
EC
n_GTX_CLK125 frequency
fG125
—
125 ± 100
ppm
—MHz
3
EC
n_GTX_CLK125 cycle time
tG125
—8
—
ns
—
EC
n_GTX_CLK125 peak-to-peak jitter
tG125J
—
250
ps
1
EC
n_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
—
55
53
%1, 2
Notes:
1. Timing is guaranteed by design and characterization.
2. EC
n_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. ECn_GTX_CLK125
duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T
reference clock.
3. ±100 ppm tolerance on EC
n_GTX_CLK125 frequency.
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