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參數(shù)資料
| 型號： | MC8640DHX1067NE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 20/130頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DUAL CORE PROCESSOR 1023-CBGA |
| 標準包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.067GHz |
| 電壓： | 0.95V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
116
Freescale Semiconductor
System Design Information
20 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8640.
20.1
System Clocking
This device includes six PLLs, as follows:
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 18.2, “MPX to SYSCLK PLL Ratio.”
The dual e600 Core PLLs generate the e600 clock from the externally supplied input.
The local bus PLL generates the clock for the local bus.
There are two internal PLLs for the SerDes block.
20.2
Power Supply Design and Sequencing
This section describes the power supply design and sequencing.
20.2.1
PLL Power Supply Filtering
Each of the PLLs listed in Section 20.1, “System Clocking,” is provided with power through independent
power supply pins.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 64, one to each of the
AVDD type pins. By providing independent filters to each PLL the opportunity to cause noise injection
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD type pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
type pin, which is on the periphery of the footprint, without the inductance of vias.
Figure 63 and Figure 64 show the PLL power supply filter circuits for the platform and cores, respectively.
Figure 63. MPC8640 PLL Power Supply Filter Circuit (for platform and Local Bus)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
AVDD_PLAT, AVDD_LB;
VDD_PLAT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8640DHX1250H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series |
| MC8640DHX1250HC | 功能描述:微處理器 - MPU G8,REV2.1,1.05V,105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8640DHX1250HE | 功能描述:微處理器 - MPU G8 REV 3.0 1.05V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8640DHX1250N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series |
| MC8640DTHX1000H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
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