參數(shù)資料
型號： MC8640DHX1067NE
廠商： Freescale Semiconductor
文件頁數(shù)： 101/130頁
文件大小： 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.067GHz
電壓： 0.95V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
72
Freescale Semiconductor
PCI Express
14.4.3
Differential Receiver (Rx) Input Specifications
Table 50 defines the specifications for the differential input at all receivers. The parameters are specified
at the component pins.
Table 50. Differential Receiver Input Specifications
Parameter
Symbol
Min
Nom
Max
Units
Comments
Unit Interval
UI
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See Note 1.
Differential
Peak-to-Peak
Output Voltage
VRX-DIFFp-p
0.175
—
1.200
V
VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|
See Note 2.
Minimum
Receiver Eye
Width
TRX-EYE
0.4
—
UI
The maximum interconnect media and
transmitter jitter that can be tolerated by the
receiver can be derived as TRX-MAX-JITTER =
1 – TRX-EYE = 0.6 UI.
See Notes 2 and 3.
Maximum time
between the jitter
median and
maximum
deviation from
the median.
TRX-EYE-MEDIAN-to-MAX
-JITTER
—
0.3
UI
Jitter is defined as the measurement variation
of the crossing points (VRX-DIFFp-p = 0 V) in
relation to a recovered Tx UI. A recovered Tx
UI is calculated over 3500 consecutive unit
intervals of sample data. Jitter is measured
using all edges of the 250 consecutive UI in
the center of the 3500 UI used for calculating
the Tx UI. See Notes 2, 3 and 7.
AC Peak
Common Mode
Input Voltage
VRX-CM-ACp
——
150
mV
VRX-CM-ACp = |VRXD+ – VRXD-|/2 – VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+ – VRX-D–|/2
See Note 2
Differential
Return Loss
RLRX-DIFF
15
—
dB
Measured over 50 MHz to 1.25 GHz with the
D+ and D– lines biased at +300 mV and
–300 mV, respectively.
See Note 4
Common Mode
Return Loss
RLRX-CM
6
—
dB
Measured over 50 MHz to 1.25 GHz with the
D+ and D– lines biased at 0 V. See Note 4
DC Differential
Input Impedance
ZRX-DIFF-DC
80
100
120
Ω
Rx DC Differential mode impedance. See
Note 5
DC Input
Impedance
ZRX-DC
40
50
60
Ω
Required Rx D+ as well as D– DC impedance
(50 ± 20% tolerance). See Notes 2 and 5.
Powered Down
DC Input
Impedance
ZRX-HIGH-IMP-DC
200
—
k
Ω
Required Rx D+ as well as D– DC impedance
when the receiver terminations do not have
power. See Note 6.
Electrical Idle
Detect Threshold
VRX-IDLE-DET-DIFFp-p
65
—
175
mV
VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ –VRX-D–|
Measured at the package pins of the receiver
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