參數(shù)資料
型號： MC8640DHX1067NE
廠商： Freescale Semiconductor
文件頁數(shù)： 30/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標準包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.067GHz
電壓： 0.95V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
125
System Design Information
Figure 69. JTAG/COP Interface Connection for Multiple MPC8640 Devices in Daisy Chain Configuration
COP_SRESET
COP_TRST
COP_HRESET
JTAG/COP
SRESET1
SRESET0
TDI
Header
HRESET
TRST
CHKSTP_OUT
CHKSTP_IN
TMS
TCK
TDO
10k
Ω
10k
Ω
SRESET1
HRESET
From Target
Board Sources
(if any)
COP_TDI
11
13
3
COP_CHKSTP_OUT
COP_CHKSTP_IN
SRESET1
SRESET0
TDI
TRST
CHKSTP_OUT
CHKSTP_IN
TMS
TCK
TDO
4
15
8
COP_TMS
2
10
COP_TCK
GND
14
9
7
6
NC
COP_VDD_SENSE
16
COP_TDO
1
3
12
2
HRESET
OVDD
SRESET0
4
10 k
Ω
Notes:
1. Populate this with a 10-
Ω resistor for short circuit/current-limiting protection.
2. KEY location; pin 14 is not physically present on the COP header.
3. Use a AND gate with sufficient drive strength to drive two inputs.
4. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order
to fully control the processor as shown above.
10k
Ω
10k
Ω
10k
Ω
10k
Ω
10k
Ω
10k
Ω
10k
Ω
6
5
10
Ω
MPC8640
3
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
6. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5
NC
1
OVDD
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