參數(shù)資料
型號(hào)： MC8640DHX1067NE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 109/130頁(yè)
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.067GHz
電壓： 0.95V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤(pán)
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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
8
Freescale Semiconductor
Electrical Characteristics
Platform supply voltage
VDD_PLAT
1.05 ± 50 mV
V
—
Local Bus and Platform PLL supply voltage
AVDD_LB,
AVDD_PLAT
1.05 ± 50 mV
V
—
DDR and DDR2 SDRAM I/O supply voltages
D1_GVDD,
D2_GVDD
2.5 V ± 125 mV
V
7
1.8 V ± 90 mV
7
eTSEC 1 and 2 I/O supply voltage
LVDD
3.3 V ± 165 mV
V
8
2.5 V ± 125 mV
V
8
eTSEC 3 and 4 I/O supply voltage
TVDD
3.3 V ± 165 mV
V
8
2.5 V ± 125 mV
V
8
Local Bus, DUART, DMA, Multiprocessor Interrupts, System
Control & Clocking, Debug, Test, Power management, I2C,
JTAG and Miscellaneous I/O voltage
OVDD
3.3 V ± 165 mV
V
5
Input voltage
DDR and DDR2 SDRAM signals
D
n
_MV
IN
GND to D
n_GVDD
V3, 6
DDR and DDR2 SDRAM reference
D
n
_MV
REF
D
n_GVDD/2 ± 1%
V
—
Three-speed Ethernet signals
LVIN
TVIN
GND to LVDD
GND to TVDD
V4, 6
DUART, Local Bus, DMA,
Multiprocessor Interrupts, System
Control & Clocking, Debug, Test,
Power management, I2C, JTAG
and Miscellaneous I/O voltage
OVIN
GND to OVDD
V5,6
Junction temperature range
TJ
0 to 105
oC—
–40 to 105
12
Notes:
1. Core 1 characteristics apply only to MPC8640D
2. If two separate power supplies are used for VDD_Core0 and VDD_Core1, they must be at the same nominal voltage and the
individual power supplies must be tracked and kept within 100 mV of each other during normal run time.
3. Caution: D
n
_MVIN must meet the overshoot/undershoot requirements for Dn_GVDD as shown in Figure 2.
4. Caution: L/TVIN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 2 during regular run time.
5. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 2 during regular run time.
6. Timing limitations for M,L,T,O)VIN and Dn_MVREF during regular run time is provided in Figure 2
7. The 2.5 V ± 125 mV range is for DDR and 1.8 V ± 90 mV range is for DDR2.
operating conditions per protocol.
9. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V. For more information refer to
10. Applies to Part Number MC8640wxx1067Nz only. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V devices. Refer to Table 74
Part Numbering Nomenclature to determine if the device has been marked for VDD_Coren = 0.95 V.
11. This voltage is the input to the filter discussed in Section 20.2, “Power Supply Design and Sequencing,” and not necessarily
the voltage at the AVDD_Coren pin, which may be reduced from VDD_Coren by the filter.
12. Applies to part number MC8640DTxxyyyyaz. Refer to Table 74 Part Numbering Nomenclature to determine if the device
has been marked for extended operating temperature range.
Table 2. Recommended Operating Conditions (continued)
Parameter
Symbol
Recommended
Value
Unit
Notes
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