參數(shù)資料
型號： MC68HSC05C9A
廠商： Motorola, Inc.
元件分類： 8位微控制器
英文描述： 8-Bit Microcontroller(8位微控制器)
中文描述： 8位微控制器（8位微控制器）
文件頁數(shù)： 93/160頁
文件大?。?/td> 783K
代理商： MC68HSC05C9A
Serial Peripheral Interface
Functional Description
MC68HC05C9A
—
Rev. 4.0
General Release Specification
MOTOROLA
Serial Peripheral Interface
93
L
G
R
10.5 Functional Description
Figure 10-2
shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the I/O operation has been
completed.
Figure 10-2. Serial Peripheral Interface Block Diagram
6
7
5
4
3
2
1
0
SPE
WCOL
BIT 6
SPIE
SPIF
BIT 7
SPI CONTROL REGISTER (SPCR)
SPI STATUS REGISTER (SPSR)
SPI DATA REGISTER (SPDR)
MSTR
MODF
BIT 4
CPOL
0
BIT 3
CPHA
0
BIT 2
SPR1
0
SPR2
0
$000A
$000B
$000C
0
BIT 5
BIT 1
BIT 0
DWOM
SPI SHIFT REGISTER
DIVIDER
÷
4
CLOCK
LOGIC
SPDR ($000C)
7 6 5 4 3 2 1 0
MODF
WCOL
SPIF
SPR1
SPR0
CPOL
CPHA
MSTR
SPE
MSTR
SPIE
PD3/
MOSI
PD2/
MISO
÷
2
÷
32
÷
16
SELECT
SPI
CONTROL
INTERNAL DATA BUS
S
M
S
M
INTERNAL
CLOCK
(XTAL
÷
2)
SPI CLOCK (MASTER)
SPI INTERRUPT REQUEST
S
PD4/
SCK
PD5/
SS
(SLAVE)
SPI
SPI
CLOCK
(MASTER)
CLOCK
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