N O N - D I S C
L O S U R E A
G
R E E M E N T R E Q U I R E D
G
M
1
I
M
I
Table 11-7. Opcode Map
Bit Manipulation
DIR
Branch
REL
Read-Modify-Write
INH
INH
Control
INH
Register/Memory
EXT
DIR
DIR
IX1
IX
INH
IMM
DIR
IX2
IX1
IX
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
5
BRSET0
3
DIR
5
5
BSET0
DIR
5
BCLR0
DIR
5
BSET1
DIR
5
BCLR1
DIR
5
BSET2
DIR
5
BCLR2
DIR
5
BSET3
DIR
5
BCLR3
DIR
5
BSET4
DIR
5
BCLR4
DIR
5
BSET5
DIR
5
BCLR5
DIR
5
BSET6
DIR
5
BCLR6
DIR
5
BSET7
DIR
5
BCLR7
DIR
2
3
BRA
2
REL
3
5
NEG
DIR
2
3
NEGA
1
INH
3
NEGX
INH
1
6
NEG
IX1
2
5
NEG
1
IX
9
RTI
INH
6
RTS
INH
1
2
SUB
2
IMM
2
3
SUB
2
DIR
3
4
SUB
3
EXT
4
5
SUB
3
IX2
5
4
SUB
2
IX1
4
3
SUB
1
IX
3
0
1
BRCLR0
3
DIR
5
2
BRN
2
REL
3
BHI
REL
3
BLS
REL
3
BCC
REL
3
BCS/BLO
2
1
CMP
2
IMM
2
CMP
2
DIR
3
CMP
3
EXT
4
CMP
3
IX2
5
CMP
2
IX1
4
CMP
1
IX
3
1
2
BRSET1
3
DIR
5
2
2
11
MUL
INH
3
COMA
INH
3
LSRA
INH
1
SBC
2
IMM
2
SBC
2
DIR
3
SBC
3
EXT
4
SBC
3
IX2
5
SBC
2
IX1
4
SBC
1
IX
3
2
3
BRCLR1
3
DIR
5
2
2
5
COM
2
DIR
1
3
COMX
1
INH
3
6
COM
IX1
6
LSR
IX1
2
5
COM
1
IX
5
10
SWI
1
INH
CPX
2
IMM
2
CPX
2
DIR
3
CPX
3
EXT
4
CPX
3
IX2
5
CPX
2
IX1
4
CPX
1
IX
3
3
4
BRSET2
3
DIR
5
2
2
5
LSR
DIR
2
1
LSRX
1
2
LSR
1
IX
AND
2
2
BIT
IMM
2
LDA
IMM
AND
2
DIR
3
BIT
DIR
3
LDA
DIR
4
STA
DIR
3
EOR
DIR
3
ADC
DIR
3
ORA
DIR
3
ADD
DIR
2
JMP
DIR
5
JSR
DIR
3
LDX
DIR
4
STX
DIR
AND
3
EXT
4
BIT
EXT
4
LDA
EXT
5
STA
EXT
4
EOR
EXT
4
ADC
EXT
4
ORA
EXT
4
ADD
EXT
3
JMP
EXT
6
JSR
EXT
4
LDX
EXT
5
STX
EXT
AND
3
IX2
5
AND
2
IX1
4
AND
1
IX
3
4
5
BRCLR2
3
DIR
5
2
REL
3
2
2
3
BIT
3
IX2
5
BIT
2
IX1
4
BIT
1
IX
3
5
6
BRSET3
3
DIR
5
2
BNE
2
REL
3
5
ROR
DIR
5
ASR
DIR
5
ASL/LSL
2
2
3
RORA
INH
3
ASRA
INH
3
ASLA/LSLA
1
INH
3
ROLA
1
INH
3
DECA
1
INH
1
3
RORX
INH
3
ASRX
INH
3
ASLX/LSLX
1
INH
3
ROLX
1
INH
3
DECX
1
INH
1
6
ROR
IX1
6
ASR
IX1
6
ASL/LSL
2
2
5
ROR
IX
1
2
2
3
LDA
IX2
6
STA
IX2
5
EOR
IX2
5
ADC
IX2
5
ORA
IX2
5
ADD
IX2
4
JMP
IX2
7
JSR
IX2
5
LDX
IX2
6
STX
IX2
3
LDA
IX1
5
STA
IX1
4
EOR
IX1
4
ADC
IX1
4
ORA
IX1
4
ADD
IX1
3
JMP
IX1
6
JSR
IX1
4
LDX
IX1
5
STX
IX1
2
LDA
IX
4
STA
IX
3
EOR
1
6
7
BRCLR3
3
DIR
5
2
BEQ
2
REL
3
2
1
1
2
5
ASR
1
IX
5
2
TAX
INH
2
CLC
INH
2
SEC
INH
2
CLI
INH
2
SEI
INH
2
RSP
INH
2
NOP
INH
1
2
3
3
2
1
7
8
BRSET4
3
DIR
5
2
BHCC
REL
3
BHCS
REL
3
BPL
REL
3
BMI
REL
3
BMC
REL
3
BMS
REL
3
BIL
REL
3
BIH
REL
2
DIR
5
IX1
6
ASL/LSL
1
IX
5
1
2
EOR
2
IMM
2
2
3
3
2
1
IX
3
8
9
BRCLR4
3
DIR
5
2
2
ROL
DIR
5
DEC
DIR
2
ROL
IX1
6
DEC
IX1
2
ROL
1
IX
5
1
ADC
2
IMM
2
2
3
3
2
ADC
1
IX
3
9
A
BRSET5
3
DIR
5
2
2
2
2
DEC
1
IX
1
ORA
2
IMM
2
2
3
3
2
ORA
1
IX
3
A
B
BRCLR5
3
DIR
5
2
2
1
ADD
2
IMM
2
3
3
2
ADD
1
IX
2
B
C
BRSET6
3
DIR
5
2
2
5
INC
DIR
4
TST
DIR
2
3
INCA
1
INH
3
3
INCX
1
INH
3
6
INC
IX1
5
TST
IX1
2
5
INC
1
IX
4
1
2
3
3
2
JMP
1
IX
5
C
D
BRCLR6
3
DIR
5
2
2
2
TSTA
INH
1
TSTX
1
INH
2
TST
1
IX
1
6
BSR
2
REL
2
2
3
3
2
JSR
IX
3
LDX
1
D
E
BRSET7
3
DIR
5
2
2
2
STOP
1
INH
2
LDX
2
IMM
2
3
3
2
1
IX
4
E
F
BRCLR7
3
DIR
2
2
5
CLR
2
DIR
3
CLRA
INH
1
3
CLRX
INH
1
6
CLR
2
IX1
5
CLR
1
IX
WAIT
1
INH
2
TXA
INH
1
2
3
3
2
STX
1
IX
F
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
0
MSB of Opcode in Hexadecimal
LSB of Opcode in Hexadecimal
0
5
BRSET0
3
DIR
Number of Cycles
Opcode Mnemonic
Number of Bytes/Addressing Mode
LSB
MSB
LSB
MSB
LSB
MSB