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參數(shù)資料
| 型號： | MC68HC705V8CFN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 52/172頁 |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC705V8CFN |
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MOTOROLA
SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 134
MC68HC705V8 Specification Rev. 2.1
15.7.5
MDLC STOP MODE
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM
bit in the MCR register is previously set. This is the lowest power mode that the MDLC can
enter.
A subsequent passive to active transition on the J1850 bus will cause the MDLC to ’wake
up’ and generate a non-maskable CPU interrupt request. The MDLC is not guaranteed to
correctly receive the message which woke it up since it may take some time for the MDLC
internal operating clocks to restart and stabilize.
When MDLC Stop mode is entered, the analog circuitry within the transmitter will be put
into a power conserving ’sleep’ mode. In MDLC Stop mode the MDLC can neither do wave
shaping nor drive any data. Therefore, it is important that the programmer ensures that all
transmissions are complete or aborted before putting the MDLC into MDLC Stop mode.
If this mode is entered while the MDLC is receiving a message, the first subsequent
received edge will cause the MDLC to immediately wake up, generate a CPU interrupt
request, and wait for the MDLC internal operating clocks to restart and stabilize before
normal communication can resume. Therefore, the MDLC is not guaranteed to correctly
receive that message.
15.7.6
MDLC WAIT MODE
This power conserving mode is automatically entered from the Run mode whenever the
CPU executes a WAIT instruction and the WCM bit in the MCR register is previously clear.
A subsequent successfully received message, including one that is in progress at the time
that this mode is entered, will cause the MDLC to ’wake up’ and generate a CPU interrupt
request if the Interrupt Enable (IE) bit in the MCR register is previously set. This results in
less of a power saving, but the MDLC is guaranteed to correctly receive the message which
woke it up since the MDLC internal operating clocks are kept running.
When MDLC Wait mode is entered, the analog circuitry within the transmitter will be put into
a power conserving ’sleep’ mode. In MDLC Wait mode the MDLC can neither do wave
shaping nor drive any data. Therefore, it is important the programmer ensures that all
transmissions are complete or aborted before putting the MDLC into MDLC Stop or MDLC
Wait mode.
15.7.7
CONTROLLING EXTERNAL VOLTAGE REGULATORS
If the application node contains other, off-chip, supply voltage regulators that need to be
controlled by J1850 network activity then an output port pin of the MCU must be reserved
by the programmer for use as a Power Sense (PSEN) signal. This pin will provide a logical
indication of when the MDLC is active through software.
Whenever the MCU is in the normal (Run) mode of operation, the programmer should
assert the PSEN output on the chosen port pin. The programmer should negate the PSEN
output just prior to placing the microcontroller in the Stop or Wait mode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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