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| 型號(hào)： | MC68HC705V8CFN |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁(yè)數(shù)： | 120/172頁(yè) |
| 文件大?。?/td> | 890K |
| 代理商： | MC68HC705V8CFN |
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MOTOROLA
SECTION 5: INTERRUPTS
Page 40
MC68HC705V8 Specification Rev. 2.1
or an MOR bit. If the EDGE sensitive interrupt option is selected for the IRQ pin, only the
IRQ latch output can activate an IRQF ag which creates an interrupt request to the CPU
to generate the external interrupt sequence.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to the following cases:
Falling edge on the IRQ pin.
Falling edge on any Port A or Port C pin with IRQ enabled.
If the LEVEL select bit in the MOR is set, the active low state of the IRQ pin can also
activate an IRQF ag which creates an IRQ request to the CPU to generate the IRQ
interrupt sequence.
When edge and level sensitivity is selected for the IRQ interrupt, it is sensitive to the
following cases:
Low level on the IRQ pin.
Falling edge on the IRQ pin.
Falling edge on any Port A or Port C pin with IRQ enabled.
The IRQE enable bit controls whether an active IRQF ag (IRQ pin interrupt) can generate
an IRQ interrupt sequence. The IRQPAE enable bit controls whether an active IRQPAF ag
(Port A interrupt) can generate an IRQ interrupt sequence. The IRQPCE enable bit controls
whether an active IRQPCF ag (Port C interrupt) can generate an IRQ interrupt sequence.
The IRQ interrupt is serviced by the interrupt service routine located at the address
specied by the contents of $3FFA and $3FFB.
The IRQF latch is automatically cleared by entering the interrupt service routine to maintain
compatibility with existing M6805 interrupt servicing protocol. To allow the user to identify
the source of the interrupt, the port interrupt flags (IRQPAF and IRQPCF) are not cleared
automatically. These flags must be cleared within the interrupt handler prior to exit in order
to prevent repeated re-entry. This is achieved by writing a logic one to the IRQA (IRQ
acknowledge) bit, which will clear all pending IRQ interrupts (including a pending IRQ pin
interrupt).
The interrupt request flags (IRQPAF and IRQPCF) are read only and cannot be cleared by
writing to them. The acknowledge flag always reads as a logic 0. Together, these features
permit the safe use of read-modify-write instructions (for example, BSET, BCLR) on the
ICSR.
NOTE:
Although read modify write instruction use is allowable on the ICSR, shift
operations should be avoided due to the possibility of inadvertently setting
the IRQA.
5.5.1
IRQ CONTROL/STATUS REGISTER (ICSR) $1F
The IRQ interrupt function is controlled by the ICSR located at $001F. All unused bits in the
ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is set by reset.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC68HC711D3CFN2 | 功能描述:IC MCU 2MHZ 4K OTP 44-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤(pán) 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱(chēng):497-9032STM32F101T8U6-ND |
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