參數(shù)資料
型號： MC68HC705V8CFN
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 152/172頁
文件大?。?/td> 890K
代理商： MC68HC705V8CFN
SECTION 9: PARALLEL I/O
MOTOROLA
Page 69
MC68HC705V8 Specification Rev. 2.1
.
Figure 9-2:
Port B I/O Circuitry
9.2.1
PORT B DATA REGISTER
Each Port B I/O pin has a corresponding bit in the Port B Data Register. When a Port B pin
is programmed as an output the state of the corresponding data register bit determines the
state of the output pin. When a Port B pin is programmed as an input, any read of the Port
B Data Register will return the logic state of the corresponding I/O pin. The Port B data
register is unaffected by reset. PB7 serves as the TCAP input and PB6 serves as the TCMP
output if the OCE bit in the MISC Register is set. See 7.2 MISCELLANEOUS REGISTER.
9.2.2
PORT B DATA DIRECTION REGISTER
Each Port B I/O pin may be programmed as an input by clearing the corresponding bit in
the DDRB, or programmed as an output by setting the corresponding bit in the DDRB. The
DDRB can be accessed at address $0005. The DDRB is cleared by reset.
9.3
PORT D AND PORT E
Port D is an 8-bit input only port that shares all of its pins with the A/D converter (AN0
through AN7) as shown in Figure 1-6. The Port D Data Register is located at address
$0003. Port E is an 8-bit input only port which also shares all of its pins with the A/D
converter (AN8 through AN15). The Port E Data Register is located at address $002B.
When the A/D converter is active, one of these 16 input ports may be selected by the A/D
multiplexer for conversion. A logical read of a selected input port will always return 0.
NOTE:
Port E is not bonded out in the 56-pin SDIP packaged version.
Read $0001
Write $0001
Read $0005
Data
Register Bit
I/O
Pin
Output
Internal HC05
Data Bus
Reset
(RST)
Write $0005
Data Direction
Register Bit
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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