參數(shù)資料
型號: MC68HC705JJ7CDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數(shù): 63/164頁
文件大?。?/td> 1165K
代理商: MC68HC705JJ7CDW
Reset Characteristics
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
155
Figure 15-13. Stop Recovery Timing Diagram
Figure 15-14. Internal Reset Timing Diagram
PCH
NEW
1FFE
t
RL
OSC1
1
RESET
INTERNAL
CLOCK(3)
INTERNAL
ADDRESS
BUS(3)
4064 or 16 t
cyc
(2)
Notes:
1. Represents the internal gating of the OSC1 pin
2. Normal delay of 4064
tcyc or short delay option of 16 tcyc
3. Internal timing signal and data information not available externally
INTERNAL
DATA
BUS(3)
1FFF
NEW PCH
NEW PCL
PCL
NEW
code
Op
PCH
NEW
1FFE
t
RPD
RESET
INTERNAL
CLOCK(3)
INTERNAL
ADDRESS
BUS(3)
4064 or 16 t
cyc
(2)
Notes:
1.Represents the internal reset from low-voltage reset, illegal opcode fetch or COP watchdog timeout
2.Only if reset occurs during normal delay of 4064 tCYC or short delay option of 16 tCYC for initial power-up
or stop recovery.
3.Internal timing signal and data information not available externally
INTERNAL
DATA
BUS(3)
1FFF
NEW PCH
NEW PCL
PCL
NEW
INTERNAL
RESET1
PIN
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參數(shù)描述
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