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參數(shù)資料
| 型號(hào)： | MC68HC705JJ7CDW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 163/164頁 |
| 文件大小： | 1165K |
| 代理商： | MC68HC705JJ7CDW |
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Simple Synchronous Serial Interface
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
98
Freescale Semiconductor
to determine the source of the interrupt and will vector to the reset vector
as a default.
SPE — Serial Peripheral Enable Bit
The SPE bit switches the port B interface such that SDO/PB5 is the serial data output, SDI/PB6 is the
serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock output in the
master mode. The port B DDR and data registers can be manipulated as usual, but these actions will
not affect the transmitted or received data. The SPE bit is readable and writable at any time, but
clearing the SPE bit while a transmission is in progress will 1) abort the transmission, 2) reset the serial
bit counter, and 3) convert port B to a general-purpose I/O port. Reset clears the SPE bit.
1 = Serial peripheral enabled (port B I/O disabled)
0 = Serial peripheral disabled (port B I/O enabled)
LSBF — Least Significant Bit First Bit
The LSBF bit controls the format of the transmitted and received data to be transferred LSB or MSB
first. Reset clears this bit.
1 = LSB transferred first
0 = MSB transferred first
MSTR — Master Mode Select Bit
The MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing to the
SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon the
divider of the oscillator frequency selected by the SPR0:1 bits. When the device is in master mode, the
SDO and SDI pins do not change function. These pins behave exactly the same in both the master
and slave modes. The MSTR bit is readable and writable at any time regardless of the state of the SPE
bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the
MSTR bit, placing the SIOP subsystem in slave mode.
1 = SIOP set up as master, SCK is an output
0 = SIOP set up as slave, SCK is an input
SPIR — Serial Peripheral Interrupt Reset Bit
The SPIR bit is a write-only control to reset the SPIF flag bit in the SSR. Reading the SPIR bit will return
a logic 0.
1 = Reset the SPIF flag bit
0 = No effect
CPHA — Clock Phase Bit
The CPHA bit controls the clock timing and phase in the SIOP. Data is changed on the falling edge of
SCK and data is captured (read) on the rising edge of SCK. This bit is cleared by reset.
1 = SCK is idle low
0 = SCK is idle high
SPR0:1 — Serial Peripheral Clock Rate Select Bits
The SPR0 and SPR1 bits select one of four clock rates given in Table 9-1 to be supplied on the
PB7/SCK pin when the device is configured with the SIOP as a master (MSTR = 1). The fastest rate
is when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared by reset, which
places the SIOP clock selection at the slowest rate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC705JP7CDW | 功能描述:IC MCU 8BIT 28-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
| MC68HC705JP7CP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HC705K1CDW | 制造商:Motorola Inc 功能描述: |
| MC68HC705KJ1CDW | 功能描述:8位微控制器 -MCU 8 Bit 4MHz RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC68HC705KJ1CP | 功能描述:IC MCU 4MHZ 1.2K OTP 16-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
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