參數(shù)資料
型號(hào)： MC68HC705JJ7CDW
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 142/164頁
文件大?。?/td> 1165K
代理商： MC68HC705JJ7CDW
Analog Status Register
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
79
ISEN
The ISEN enable bit will power down the charge current source and disable the discharge device in
the analog subsystem. Powering down the current source will drop the supply current by about 200
A. This bit is cleared by a reset of the device.
1 = Writing a logic 1 powers up the ramping current source and enables the discharge device on
the PB0/AN0 pin.
0 = Writing a logic 0 powers down the ramping current source and disables the discharge device on
the PB0/AN0 pin.
NOTE
The analog subsystem has support circuitry which draws current. This
current will be powered down if both comparators and the charge current
source are powered down (ISEN, CP1EN, and CP2EN all cleared).
Powering up either comparator or the charge current source will activate
the support circuitry.
8.4 Analog Status Register
The analog status register (ASR) contains status and control of the comparator flag bits. These bits in the
ASR are shown in Figure 8-6. All the bits in this register are cleared by a reset of the device.
CPF2
This read-only flag bit is edge sensitive to the rising output of comparator 2. It is set when the voltage
on the PB0/AN0 pin rises above the voltage on a sample capacitor which creates a positive edge on
the output of comparator 2, regardless of the state of the INV bit in the AMUX register. This bit is reset
by writing a logic 1 to the CPFR2 reset bit in the ASR. This bit is cleared by a reset of the device.
1 = A positive transition on the output of comparator 2 has occurred since the last time the CPF2
flag has been cleared.
0 = A positive transition on the output of comparator 2 has not occurred since the last time the CPF2
flag has been cleared.
CPF1
This read-only flag bit is edge sensitive to the rising output of comparator 1. It is set when the voltage
on the PB2/AN2 pin rises above the voltage on the PN3/AN3/TCAP pin which creates a positive edge
on the output of comparator 1, regardless of the state of the INV bit in the AMUX register. This bit is
reset by writing a logic 1 to the CPFR1 reset bit in the ASR. This bit is cleared by a reset of the device.
1 = A positive transition on the output of comparator 1 has occurred since the last time the CPF1
flag has been cleared.
0 = A positive transition on the output of comparator 1 has not occurred since the last time the CPF1
flag has been cleared.
Address:
$001E
Bit 7
654321
Bit 0
Read:
CPF2
CPF1
0
COE1
VOFF
CMP2
CMP1
Write:
CPFR2
CPFR1
R
Reset:
00000000
= Unimplemented
R
= Reserved
Figure 8-6. Analog Status Register (ASR)
相關(guān)PDF資料
PDF描述
MC68HC705JJ7CP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20
MC68HC705JJ7S 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
MC68HC705K1DWR2 8-BIT, OTPROM, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, MICROCONTROLLER, PDIP16
MC68HC705K1P 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MC68HC705JP7CP 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述:
MC68HC705K1CDW 制造商:Motorola Inc 功能描述:
MC68HC705KJ1CDW 功能描述:8位微控制器 -MCU 8 Bit 4MHz RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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