MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
95
Chapter 9
Simple Synchronous Serial Interface
9.1 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial
communications with peripheral devices or other MCUs. SIOP is implemented as a 3-wire master/slave
system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block diagram of
Figure 9-1. SIOP Block Diagram
PORTB LOGIC
SIOP
INTERRUPT
PB7
SCK
PB6
SDI
PB5
SDO
SDR0
SDR1
SDR2
SDR3
SDR4
SDR5
SDR6
SDR7
SIOP
INT
E
RNAL
M68
HC05
BUS
SPE
SIOP
CON
T
ROL
REGIS
TER
(SCR)
SPIE
DATA REGISTER
(SDR)
DCOL
SIOP
STATUS
REGISTER
(SSR)
SPIF
FORMAT CONTROL
SPIR
8-BIT SHIFT
LSBF
LATCH
S
R
REGISTER
DIN
DOUT
CLK
CLOCK
CONTROL
MSTR
CPHA
SPR1
SPR0
CLOCK
DIVIDER
OSCILLATOR
CLOCK
Q
(LSB OR MSB FIRST)
PORTB LOGIC
AND
SELECT
D0
D1
D2
D3
D4
D5
D6
D7
INTERNAL M68HC05 BUS
COMP
ERROR
÷2
$000A
$000B
$000C