參數資料
型號: MC68HC705JB2P
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數: 93/128頁
文件大?。?/td> 2493K
代理商: MC68HC705JB2P
August 28, 1998
GENERAL RELEASE SPECIFICATION
PROGRAMMABLE TIMER
REV 1.1
9-9
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
This read/write bit enables interrupts caused by a successful compare between
the timer counter and the output compare registers. Reset clears the OCIE bit.
1 =
Output compare interrupts enabled.
0 =
Output compare interrupts disabled.
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
This read/write bit enables interrupts caused by a timer overow. Reset clears
the TOIE bit.
1 =
Timer overow interrupts enabled.
0 =
Timer overow interrupts disabled.
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative
transition on the TCAP pin triggers a transfer of the contents of the timer
register to the input capture register. Reset has no effect on the IEDG bit.
1 =
Positive edge (low to high transition) triggers input capture.
0 =
Negative edge (high to low transition) triggers input capture.
9.6
TIMER STATUS REGISTER (TSR)
The timer status register (TSR) shown in Figure 9-11 contains ags for the
following events:
An active signal on the PB0/TCAP pin, transferring the contents of the
timer registers to the input capture registers.
A match between the 16-bit counter and the output compare registers
An overow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the TSR has no effect. Reset does not change the
state of any of the ag bits in the TSR.
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB0/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICRL, $0015) of the input capture
registers. Reset has no effect on ICF.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TSR
R
ICF
OCF
TOF
00000
$0013
W
reset:
U
00000
U = UNAFFECTED BY RESET
Figure 9-11. Timer Status Registers (TSR)
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相關PDF資料
PDF描述
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