參數(shù)資料
型號： MC68HC705JB2P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁數(shù)： 90/128頁
文件大?。?/td> 2493K
代理商： MC68HC705JB2P
GENERAL RELEASE SPECIFICATION
August 28, 1998
PROGRAMMABLE TIMER
MC68HC705JB2
9-6
REV 1.1
trigger to improve noise immunity. The edge that triggers the counter transfer is
dened by the input edge bit (IEDG) in the TCR. Reset does not affect the
contents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
Reading the ICRH inhibits further captures until the ICRL is also read. Reading
the ICRL after reading the timer status register (TSR) clears the ICF ag bit. does
not inhibit transfer of the free-running counter. There is no conict between
reading the ICRL and transfers from the free-running timer counters. The input
capture registers always contain the free-running timer counter value which
corresponds to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH
and ICRL, set the I bit in the condition code register (CCR) before
reading ICRH and clear the I bit after reading ICRL.
9.4
OUTPUT COMPARE REGISTERS
The Output Compare function is a means of generating an interrupt when the 16-
bit timer counter reaches a selected value as shown in Figure 9-8. Software
writes the selected value into the output compare registers. On every fourth
internal clock cycle (every eight oscillator clock cycle) the output compare circuitry
compares the value of the free-running timer counter to the value written in the
output compare registers. When a match occurs, the output compare interrupt
ag, OCF is set. A timer interrupt request to the CPU is generated if the output
compare interrupt enable is set, i.e. OCIE=1.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICRH
R
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
$0014
W
reset:
UUUUUUUU
ICRL
R
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
$0015
W
reset:
UUUUUUUU
U = UNAFFECTED BY RESET
Figure 9-7. Input Capture Registers (ICRH, ICRL)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
MC68HC705K1CDW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1S 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, CDIP16
MC68HC705K1DW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MC68HC705JP7CDW 功能描述:IC MCU 8BIT 28-SOIC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND
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MC68HC705K1CDW 制造商:Motorola Inc 功能描述:
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