參數(shù)資料
型號(hào)： MC68HC705JB2P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁數(shù)： 124/128頁
文件大?。?/td> 2493K
代理商： MC68HC705JB2P
August 28, 1998
GENERAL RELEASE SPECIFICATION
UNIVERSAL SERIAL BUS MODULE
REV 1.1
10-27
10.6
USB INTERRUPTS
The USB module is capable of generating interrupts and causing the CPU to
execute the USB interrupt service routine. There are three types of USB
interrupts:
End of Transaction interrupts signify a completed transaction (receive or
transmit)
Resume interrupts signify that the USB bus is reactivated after having
been suspended
End of Packet interrupts signify that a low speed end of packet signal
was detected
All USB interrupts share the same interrupt vector. Firmware is responsible for
determining which interrupt is active.
10.6.1 USB End of Transaction Interrupt
There are three possible end of transaction interrupts: Endpoint 0 Receive,
Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of
transaction interrupts occur as detailed in the following sections.
10.6.1.1 Receive Control Endpoint 0
For a Control OUT transaction directed at Endpoint 0, the USB module will
generate an interrupt by setting the RXD0F ag in the UIR0 register. The
conditions necessary for the interrupt to occur are shown in the owchart of
SETUP transactions cannot be stalled by the USB function. A SETUP received by
a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving
a SETUP interrupt are shown in Figure 10-30.
10.6.1.2 Transmit Control Endpoint 0
For a Control IN transaction directed at Endpoint 0, the USB module will generate
an interrupt by setting the TXD0F ag in the UIR0 register. The conditions
necessary for the interrupt to occur are shown in the owchart of Figure 10-31.
10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2
Transmit Endpoints 1 & 2 share their interrupt ag. For an IN transaction directed
at Endpoint 1 or 2, the USB module will generate an interrupt by setting the
TXD1F ag in the UIR1 register. The conditions necessary for the interrupt to
occur are shown in the owchart of Figure 10-32.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
MC68HC705JB4P 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP28
MC68HC705K1CDW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1S 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, CDIP16
MC68HC705K1DW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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