參數(shù)資料
型號(hào)： MC68HC705CL4FU
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 75/101頁(yè)
文件大?。?/td> 517K
代理商： MC68HC705CL4FU
February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
INSTRUCTION SET
MOTOROLA
REV 2.0
11-1
SECTION 11
INSTRUCTION SET
This section describes the addressing modes and instruction types.
11.1
ADDRESSING MODES
The CPU uses eight addressing modes for exibility in accessing data. The
addressing modes dene the manner in which the CPU nds the data required to
execute an instruction. The eight addressing modes are the following:
Inherent
Immediate
Direct
Extended
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
Relative
11.1.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt
(RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU
registers, such as set carry ag (SEC) and increment accumulator (INCA). Inher-
ent instructions require no memory address and are one byte long.
11.1.2 Immediate
Immediate instructions are those that contain a value to be used in an operation
with the value in the accumulator or index register. Immediate instructions require
no memory address and are two bytes long. The opcode is the rst byte, and the
immediate data value is the second byte.
11.1.3 Direct
Direct instructions can access any of the rst 256 memory addresses with two
bytes. The rst byte is the opcode, and the second is the low byte of the operand
address. In direct addressing, the CPU automatically uses $00 as the high byte of
the operand address. BRSET and BRCLR are three-byte instructions that use
direct addressing to access the operand and relative addressing to specify a
branch destination.
相關(guān)PDF資料
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