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參數(shù)資料
| 型號： | MC68HC705CL4FU |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 51/101頁 |
| 文件大?。?/td> | 517K |
| 代理商： | MC68HC705CL4FU |
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February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
TIMERS
MOTOROLA
REV 2.0
8-11
ICF—Input Capture Flag
The input capture ag (ICF) is set when a proper edge has been sensed by the
input capture edge detector. It is cleared by a processor access of the timer
status register (with ICF set) followed by accessing the low byte ($15) of the
input capture register. Reset does not affect the input compare ag.
OCF—Output Compare Flag
The output compare ag (OCF) is set when the output compare register con-
tents matches the contents of the free running counter. The OCF is cleared by
accessing the timer status register (with OCF set) and then accessing the low
byte ($17) of the output compare register. Reset does not affect the output
compare ag.
TOF—Timer Overow Flag
The timer overow ag (TOF) bit is set by transition of the free run from $FFFF
to $0000. It is cleared by accessing the timer status register (with TOF set) fol-
lowed by an access of the free running counter least signicant byte ($19).
Reset does not affect the TOF bit.
Accessing the timer status register satises the rst condition required to clear
status bits. The remaining step is to access the register corresponding to the sta-
tus bit.
A problem can occur when using the timer overow function and reading the free-
running counter at random times to measure an elapsed time. Without incorporat-
ing the proper precautions into software, the timer overow ag could unintention-
ally be cleared if: 1)The timer status register is read or written when TOF is set,
and 2)The LSB of the free-running counter is read but not for the purpose of ser-
vicing the ag. The counter alternate register at address $1A and $1B contains
the same value as the free-running counter (at address $18 and $19); therefore,
this alternate register can be read at any time without affecting the timer overow
ag in the timer status register.
8.1.6 Operation During Low Power Mode
During the wait and stop modes, the timer stops and holds at its current state,
retaining all data, and resumes operation from this point when external interrupt
(IRQ), or internal interrupt is received.
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