參數(shù)資料
型號(hào)： MC68HC705CL4FU
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 1.84 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 40/101頁(yè)
文件大小： 517K
代理商： MC68HC705CL4FU
February 12, 1997
GENERAL RELEASE SPECIFICATION
MC68HC05CL4
TIMERS
MOTOROLA
REV 2.0
8-1
SECTION 8
TIMERS
The MCU has two independent timers, the multi-functional timer and the core
timer.
8.1
MULTI-FUNCTIONAL TIMER
The timer consists of a 16-bit free-running counter driven by a xed divide-by-four
prescaler. This timer can be used for many purposes, including input waveform
measurements while simultaneously generating an output waveform. Pulse widths
can vary from several microseconds to many seconds. Refer to Figure 8-1 for a
timer block diagram.
Because the timer has a 16-bit architecture, each specic functional segment
(capability) is represented by two registers. These registers contain the high and
low byte of that functional segment. Generally, accessing the low byte of a specic
timer function allows full control of that function; however, an access of the high
byte inhibits that specic timer function until the low byte is also accessed.
NOTE
The I-bit in the CCR should be set while manipulating both the high and low byte
register of a specic timer function to ensure that an interrupt does not occur.
8.1.1 Counter
The key element in the programmable timer is a 16-bit, free-running counter or
counter register, preceded by a prescaler that divides the internal processor clock
by four. The prescaler gives the timer a resolution of 2 microseconds if the internal
bus clock is 2.0 MHz. The counter is incremented during the low portion of the
internal bus clock. Software can read the counter at any time without affecting its
value.
The double-byte, free-running counter can be read from either of two locations,
$18-$19 (counter register) or $1A-$1B (counter alternate register). A read from
only the least signicant byte (LSB) of the free-running counter ($19, $1B)
receives the count value at the time of the read. If a read of the free-running
counter or counter alternate register rst addresses the most signicant byte
(MSB) ($18, $1A), the LSB ($19, $1B) is transferred to a buffer. This buffer value
remains xed after the rst MSB read, even if the user reads the MSB several
times. This buffer is accessed when reading the free-running counter or counter
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