參數(shù)資料
型號: MC68HC16S2CPU25
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 25.17 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁數(shù): 27/104頁
文件大?。?/td> 812K
代理商: MC68HC16S2CPU25
MC68HC16S2
MOTOROLA
MC68HC16S2TS/D
29
Figure 11 Chip-Select Circuit Block Diagram
When a memory access occurs, chip-select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select sig-
nals are active low. If a chip-select function is given the same address as a microcontroller module or
an internal memory array, an access to that address goes to the module or array, and the chip-select
signal is not asserted. The external address and data buses do not reflect the internal access.
All chip-select circuits except CSBOOT are disabled out of reset. Chip-select option registers must not
be written until base addresses have been written to the proper base address registers. Alternate func-
tions for chip-select pins are enabled if appropriate data bus pins are held low at the release of RESET.
Table 17 lists allocation of chip-selects and discrete outputs on the pins of the MCU.
Table 17 Chip-Select and Discrete Output Allocation
Pin
Chip-Select
Discrete Outputs
CSBOOT
BR
CS0
BG
CS1
BGACK
CS2
FC0
CS3
PC0
FC1
CS4
PC1
FC2
CS5
PC2
ADDR19
CS6
PC3
ADDR20
CS7
PC4
ADDR21
CS8
PC5
ADDR22
CS9
PC6
ADDR23
CS10
CHIP-SEL BLOCK
AVEC
GENERATOR
DSACK
GENERATOR
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
BASE ADDRESS REGISTER
TIMING
AND
CONTROL
ADDRESS COMPARATOR
OPTION COMPARE
OPTION REGISTER
AVEC
DSACK
PIN
BUS CONTROL
INTERNAL
SIGNALS
ADDRESS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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