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| 型號(hào)： | MC68HC16S2CPU25 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 25.17 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 24/104頁 |
| 文件大?。?/td> | 812K |
| 代理商： | MC68HC16S2CPU25 |
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MOTOROLA
MC68HC16S2
26
MC68HC16S2TS/D
The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence
of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with
these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be
used to generate the BERR signal for internal-to-external transfers. When BERR and HALT are assert-
ed simultaneously, the CPU takes a bus error exception.
The autovector signal (AVEC) can terminate IRQ pin interrupt acknowledge cycles. AVEC indicates that
the MCU will internally generate a vector number to locate an interrupt handler routine. If it is continu-
ously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored during
all other bus cycles.
3.5.8 Dynamic Bus Sizing
The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing
operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device sig-
nals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK1
and DSACK0 inputs, as shown in Table 15.
For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port,
the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits.
The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the
DSACK0 and DSACK1 signals to indicate the port width. For instance, a 16-bit device always returns
DSACK0 = 1 and DSACK1 = 0 for a 16-bit port, regardless of whether the bus cycle is a byte or word
operation.
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular
port size be fixed. A 16-bit port must reside on data bus bits [15:0] and an 8-bit port must reside on data
bus bits [15:8]. This minimizes the number of bus cycles needed to transfer data and ensures that the
MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles. For a word oper-
ation, it is assumed that the port is 16 bits wide when the bus cycle begins. Operand bytes are desig-
nated as shown in Figure 10. OP0 is the most significant byte of a long-word operand, and OP3 is the
least significant byte. The two bytes of a word-length operand are OP0 (most significant) and OP1. The
single byte of a byte-length operand is OP0.
Table 15 Effect of DSACK Signals
DSACK1
DSACK0
Result
1
Insert wait states in current bus cycle
1
0
Complete cycle — Data bus port size is 8 bits
0
1
Complete cycle — Data bus port size is 16 bits
0
Reserved
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MC68HC16Z1CAG | 制造商:Freescale Semiconductor 功能描述: |
| MC68HC16Z1CAG16 | 功能描述:16位微控制器 - MCU 16 BIT MCU 1K RAM RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
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