參數(shù)資料
型號(hào): MC68HC16S2CPU25
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, 25.17 MHz, MICROCONTROLLER, PQFP100
封裝: TQFP-100
文件頁(yè)數(shù): 15/104頁(yè)
文件大小: 812K
代理商: MC68HC16S2CPU25
MOTOROLA
MC68HC16S2
18
MC68HC16S2TS/D
3.3.5.1 LPSTOP Mode
This low power mode offers the greatest power reduction. To enter normal LPSTOP mode, the CPU16
executes the LPSTOP instruction after clearing the STCPU bit in SYNCR. This causes the SIM to turn
off the system clock to most of the MCU.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of the current interrupt
mask into the clock control logic. The SIM brings the MCU out of normal LPSTOP mode when one of
the following exceptions occurs:
RESET
Trace
SIM interrupt of higher priority than the stored interrupt mask
During LPSTOP, unless the system clock signal is supplied by an external source and that source is
removed, the SIM clock control logic and the SIM clock signal (SIMCLK) continue to operate. The peri-
odic interrupt timer and input logic for the RESET and IRQ pins are clocked by SIMCLK, and can be
used to bring the processor out of LPSTOP. The software watchdog monitor cannot perform this func-
tion. Optionally, the SIM can also continue to generate the CLKOUT signal while in LPSTOP.
STSIM and STEXT bits in SYNCR determine clock operation during LPSTOP.
The flow chart shown in Figure 8 summarizes the effects of the STSIM and STEXT bits when the MCU
enters normal LPSTOP mode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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