MOTOROLA
12-14
CONFIGURABLE TIMER MODULE 7
MC68HC16R1/916R1
USER’S MANUAL
12.9.1 DASM Interrupts
The DASM can optionally request an interrupt when the FLAG bit in DASMSIC is set.
To enable interrupts, set the IL[2:0] field in DASMSIC to a non-zero value. The CTM7
compares the CPU16 IP mask value to the priority of the requested interrupt designat-
ed by IL[2:0] to determine whether it should contend for arbitration priority. During ar-
bitration, the BIUSM provides the arbitration value specified by IARB[2:0] in BIUMCR
and IARB3 in DASMSIC. If the CTM7 wins arbitration, it responds with a vector num-
ber generated by concatenating VECT[7:6] in BIUMCR and the six low-order bits
specified by the number of the submodule requesting service. Thus, for DASM9 in the
CTM7, the six low-order bits would be nine in decimal, or %001001 in binary.
12.9.2 DASM Registers
The DASM contains one status/interrupt/control register and two data registers (A and
B). All unused bits and reserved address locations return zero when read. Writes to
unused bits and reserved address locations have no effect. The CTM7 contains four
DASMs, each with its own set of registers. Refer to
D.7.11 DASM Status/Interrupt/
Control Registers
,
D.7.12 DASM Data Register A
, and
D.7.13 DASM Data Register
B
for information concerning DASM register and bit descriptions.
12.10 Pulse-Width Modulation Submodule (PWMSM)
The PWMSM allows pulse width modulated signals to be generated over a wide range
of frequencies, independently of other CTM7 output signals. The output pulse width
duty cycle can vary from 0% to 100%, with 16 bits of resolution. The minimum pulse
width is twice the MCU system clock period. For example, the minimum pulse width is
119 ns when using a 16.78 MHz clock.
The PWMSM is composed of:
An output flip-flop with output polarity control
Clock prescaler and selection logic
A 16-bit up-counter
Two registers to hold the current and next pulse width values
Two registers to hold the current and next pulse period values
A pulse width comparator
A system state sequencer
Logic to create 0% and 100% pulses
Interrupt logic
A status, interrupt and control register
A submodule bus interface
The PWMSM includes its own time base counter and does not use the CTM7 time
base buses; however, it does use the prescaled clock signal PCLK1 generated by the
CPSM. Refer to
12.5 Counter Prescaler Submodule (CPSM)
and
Figure 12-1
for
more information.
Figure 12-7
shows a block diagram of the PWMSM.