參數(shù)資料
型號(hào): MC68HC11P3CFN4R2
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQCC84
封裝: PLASTIC, LCC-84
文件頁(yè)數(shù): 32/236頁(yè)
文件大小: 1232K
代理商: MC68HC11P3CFN4R2
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MC68HC11P2
MOTOROLA
8-5
TIMING SYSTEM
8
8.2
Input capture
The input capture function records the time an external event occurs by latching the value of the
free-running counter when a selected edge is detected at the associated timer input pin. Software
can store latched values and use them to compute the periodicity and duration of events. For
example, by storing the times of successive edges of an incoming signal, software can determine
the period and pulse width of a signal. To measure period, two successive edges of the same
polarity are captured. To measure pulse width, two alternate polarity edges are captured.
In most cases, input capture edges are asynchronous with respect to the internal timer counter,
which is clocked relative to an internal clock (PH2). These asynchronous capture requests are
synchronized with PH2 so that latching occurs on the opposite half cycle of PH2 from when the
timer counter is being incremented. This synchronization process introduces a delay from when
the edge occurs to when the counter value is detected. Because these delays cancel out when
the time between two edges is being measured, the delay can be ignored. When an input capture
is being used with an output compare, there is a similar delay between the actual compare point
and when the output pin changes state.
The control and status bits that implement the input capture functions are contained in the PACTL,
TCTL2, TMSK1, and TFLG1 registers.
To congure port A bit 3 as an input capture, clear the DDA3 bit of the DDRA register. Note that
this bit is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the
PACTL register. Otherwise, PA3 is congured as a fth output compare out of reset, with bit I4/O5
being cleared. If the DDA3 bit is set (conguring PA3 as an output), and IC4 is enabled, then writes
to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the
TI4/O5 register is acting as IC4.
8.2.1
TCTL2 — Timer control register 2
Use the control bits of this register to program input capture functions to detect a particular edge
polarity on the corresponding timer input pin. Each of the input capture functions can be
independently congured to detect rising edges only, falling edges only, any edge (rising or falling),
or to disable the input capture function. The input capture functions operate independently of each
other and can capture the same TCNT value if the input edges are detected within the same timer
count cycle.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer control 2 (TCTL2)
$0021
EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000
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