
MOTOROLA
ii
MC68HC11P2
INDEX
clocks -
continued
SPI 7-4
ST4XCK 6-7
stretching 3-17
timer divider chains
8-3
CME - bit in OPTION 10-4
coherency, timer 8-8
CON12 - bit in PWCLK 8-23
CON34 - bit in PWCLK 8-23
concatenation, of PWM 8-23
CONFIG — System configuration reg. 3-12
CONFIG, programming 3-26
configuration 3-12
conversion, A/D 9-3
, 9-4, 9-4, 9-5
COP 8-1
, 8-16
CONFIG — Configuration control reg. 10-5
COPRST — Arm/reset COP timer circuitry reg. 10-3
enable 10-5
OPTION — System configuration options reg. 1 10-3
rates 10-4
reset 10-2
, 10-3, 10-7
timeout 10-2
COPRST — Arm/reset COP timer circuitry reg. 10-3
corruption
of A/D 4-6
of memory 2-3
CPHA - bit in SPCR 7-3
, 7-4, 7-7
CPOL - bit in SPCR 7-6
CPU
accumulators (A, B and D) 11-2
architecture 11-1
CCR — Condition code reg. 11-4
index registers (IX, IY) 11-2
program counter (PC) 11-4
programming model
11-1
registers 11-1
reset 10-6
stack pointer (SP) 11-2
CR[1:0] - bits in OPTION 10-4
CSEL - bit in OPTION 9-6
CWOM - bit in OPT2 3-17
, 4-11
D
DAC 9-3
data format, SCI 5-2
data types 11-6
DDA[7:0] - bits in DDRA 4-2
DDB[7:0] - bits in DDRB 4-3
DDC[7:0] - bits in DDRC 4-4
DDD[5:0] - bits in DDRD 4-5
DDF[7:0] - bits in DDRF 4-7
DDG[7:0] - bits in DDRG 4-8
DDH[7:0] - bits in DDRH 4-9
DDRA — Data direction reg. for port A 4-2
DDRB — Data direction reg. for port B 4-3
DDRC — Data direction reg. for port C 4-4
DDRD — Data direction reg. for port D 4-5
DDRF — Data direction reg. for port F 4-7
DDRG — Data direction reg. for port G 4-8
DDRH — Data direction reg. for port H 4-9
development tools 15-1
DIR - direct addressing mode 11-7
DISCP - bit in PWEN 8-26
DLY - bit in OPTION 3-16
, 9-6
duty cycle, PWM 8-28
DWOM - bit in SPCR 7-6
E
E clock pin 2-5
EDGxA and EDGxB - bits in TCTL2 8-6
EELAT - bit in PPROG 3-24
EEON - bit in CONFIG 3-13
EEPGM - bit in PPROG 3-24
EEPROM 3-23
–3-26
erased state ($FF) 3-23
erasing 3-25
–3-26
PPROG — EEPROM programming control reg. 3-23
security 3-27
ELAT - bit in EPROG 3-21
EPGM - bit in EPROG 3-22
EPROG — EPROM programming control reg. 3-21
EPROM 3-5
, 3-21–3-22
device 1-1
EPROG — EPROM programming control reg. 3-21
erased state ($FF) 3-21
programming 3-22
ERASE - bit in PPROG 3-24
erased state
EEPROM ($FF) 3-23
EPROM ($FF) 3-21
error detection, SCI 5-5
ESD protection 12-1
EVEN - bit in PPROG 3-23
event counter - see pulse accumulator
EVS — Evaluation system 15-1
EXCOL - bit in EPROG 3-21
EXROW - bit in EPROG 3-22
EXT - extended addressing mode 11-8
EXTAL pin 2-4
F
FCME - bit in OPTION 10-4
FE - bit in SCSR1 5-10
FOC[1:5] - bits in CFORC 8-9
FPPUE - bit in PPAR 4-10
free-running counter 8-1