- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67966 > MC68HC11G5CFN (ABILIS SYSTEMS) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC11G5CFN |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 40/195頁(yè) |
| 文件大?。?/td> | 3620K |
| 代理商： | MC68HC11G5CFN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)當(dāng)前第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)
EVENT COUNTER
11-4
The two counter registers (EVCNT1 and EVCNT2) are clocked by the same signal via the INPUT1
selector. This clock signal can be the E-clock, a scaled E-clock or an external signal applied to the
EVI1 pin. If the clock signal is the E-clock or a derivative, an external gating signal can be applied
to EVI1. If EVI1 is not used for clock or gate, it can be used as a normal I/O pin (PH5).
The 8-bit phase shift value (X) is stored in ECMP2A (in the PA unit). When the count in EVCNT2
reaches this value, the successful compare causes a clearing signal to be applied to EVCNT1 in the
PWM unit and starts the PWM sequence.
The value of the output pulse width (Y) is stored in ECMP1A, however the start time and the duration
of this pulse can be modified by a skew value (X’) which is stored in ECMP1B. If no skew is included,
i.e. ECMP1B is set to zero, then a compare occurs when EVCNT1 is cleared, and the output signal
changes state immediately after the initial phase shift period X introduced by the PA unit. The effect
of storing a skew value (X’) in ECMP1B is to delay the leading edge of the PWM output pulse by the
phase shift plus the skew value (X+X’).
The trailing edge of the output pulse is generated when there is a match between EVCNT1 and
ECMP1A (X + Y). Note that the skew value does not affect the timing of the trailing edge of the output
pulse, but only the leading edge. Consequently the output pulse width is reduced by the skew value
from Y to Y-X’. A maskable interrupt signal EVENT1 is generated when there is a match between
EVCNT1 and ECMP1A.
A clearing signal on the EVI2 pin clears EVCNT2 in the PA unit and restarts the sequence.
ECMP2B can be used to generate an interrupt signal, EVENT2, when EVCNT2 accumulates a
desired number of clock pulses.
11.2.2
Register Functions in Mode 0
11.2.2.1
Counter 1 (EVCNT1)
This counter drives the PWM section of the event counter. It is cleared by a successful comparison
between ECMP2A and EVCNT2. The source chosen by input selector INPUT1 is used as the clock
input to both counters (EVCNT1 and EVCNT2). The width and time of the output pulse is determined
by the value in this counter matching the values in ECMP1A and ECMP1B.
11.2.2.2
Compare Register 1A (ECMP1A); (Y)
This compare register holds the nominal value of the output pulse width. Note that the actual output
pulse width value will be equal to the value contained in ECMP1A minus the skew value which is
held in event compare register 1B (ECMP1B). An interrupt signal, EVENT1 is generated when there
is a match between ECMP1A and EVCNT1.
11.2.2.3
Compare Register 1B (ECMP1B); (X’)
This compare register holds a value which adjusts the phase skew between the external signal (on
EVI2) and the leading edge of the desired output signal. If the value in this register is zero, then the
actual pulse width depends only on the value Y in ECMP1A. If the value in this register is equal to
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC11L6VFU23 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC11L6CFU22 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC11L6VFU22 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC11L6MFU22 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| MC68HC11L6MFU23 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11G7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Unit |
| MC68HC11G7CFN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| MC68HC11K0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC11K0CFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11K0CFN3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。