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| 型號(hào)： | MC68HC11G5CFN |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁(yè)數(shù)： | 135/195頁(yè) |
| 文件大小： | 3620K |
| 代理商： | MC68HC11G5CFN |
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INPUT/OUTPUT PORTS
4-6
Port D bit 1 becomes the Transmit Data output (TXD) when the SCI transmitter is enabled (TE bit
in the SCCR2 register set to one). When the TE bit is clear, Port D bit 1 defaults to being a general
purpose I/O pin controlled by DDRD. Note that the transmit logic will retain control of Port D bit 1 after
TE is cleared until all transmit operations have finished, including completion of transmission of data
from the serial shifter, a queued idle, or queued break.
In a test mode, the RCKB test bit in the BAUD register may be set. When RCKB is set, the 16X
receiver baud rate clock and the 1X transmitter clock are exclusive-ORed and driven out of the Port
D bit 1 pin. The RCKB bit can be written only in the test or bootstrap modes and it overrides any other
use of the Port D bit 1 pin.
Bits 2 – 5 of Port D are dedicated to the serial peripheral interface function (SPI) whenever the SPE
bit in the SPCR register is set (SPI enabled). Note that Port D bit 5 still responds to DDRD bit 5 such
that, if the DDR bit is set, the Port D bit 5 pin is given up by the SPI system to become a general
purpose output pin if and only if the SPI is in master mode. When the SPE bit is clear, bits 2 – 5 of
Port D default to being general purpose I/O pins controlled by DDRD.
The four SPI interface lines are described in greater detail in SECTION 8: SERIAL PERIPHERAL
INTERFACE.
4.7.1
Data Register (PORTD)
0
PD5
PD4
PD3
PD2
PD1
PD0
PORTD
$1008
7
6
5
4
3
2
1
0
RESET:
Alternate Pin Function:
—
SS
SCK
MOSI
MISO
TXD
RXD
READ:
Any time (inputs return pin level; outputs return pin driver input level). Bits 6 and 7 always
read as zeros.
WRITE:
Data stored in internal latch (drives pins only if configured as outputs). Writes to bit 6 and
7 have no meaning or effect.
RESET:
Bits 0 – 5 are configured as general purpose inputs.
4.7.2
Data Direction Register (DDRD)
0
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
DDRD
$1009
7
6
5
4
3
2
1
0
RESET:
READ:
Any time (reads of bits 6 and 7 always return zeros).
WRITE:
Any time (writes to bits 6 and 7 have no meaning or effect).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MC68HC11G7 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Unit |
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| MC68HC11K0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit |
| MC68HC11K0CFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11K0CFN3 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller |
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