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參數(shù)資料
| 型號： | MC68HC11G5CFN |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 191/195頁 |
| 文件大?。?/td> | 3620K |
| 代理商： | MC68HC11G5CFN |
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SERIAL COMMUNICATIONS INTERFACE
7-5
The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2
register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE)
are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU
bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do
so. Normally RWU is set by software and gets cleared automatically with hardware by one of the
two methods described below.
7.4.1
Idle Line Wake-up
In idle line wake-up mode, a dormant receiver wakes up as soon as the RXD line becomes idle. Idle
is defined as a continuous logic high level on the RXD line for ten (or eleven) full bit times. Systems
using this type of wake-up must provide at least one character time of idle between messages to
wake up sleeping receivers, but must not allow any idle time between characters within a message.
7.4.2
Address Mark Wake-up
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate that the
character is an address (1) or a data (0) character. Sleeping receivers will wake up whenever an
address character is received. Systems using this method for wake-up would set the MSB of the first
character of each message and leave it clear for all other characters in the message. Idle periods
may be present within messages and no idle time is required between messages for this wake-up
method.
7.5
RECEIVE DATA (RXD)
Receive data is the serial data that is applied through the input line and the serial communications
interface to the internal bus. The receiver circuitry clocks the input at a rate equal to 16 times the
baud rate and this time is referred to as the RT clock.
Once a valid start bit is detected the start bit, each data bit and the stop bit are sampled three times
at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start), as shown
in Figure 7-4. The value of the bit is determined by voting logic which takes the value of the majority
of the samples.
RxD
Previous Bit
Present Bit
Samples
Next Bit
vvv
16
1
R
T
R
T
16
1
R
T
R
T
89
10
R
T
R
T
R
T
Figure 7-4. Sampling Technique Used On All Bits
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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