參數(shù)資料
型號(hào): MC68HC05F8B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁(yè)數(shù): 84/126頁(yè)
文件大小: 736K
代理商: MC68HC05F8B
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MOTOROLA
6-12
MC68HC05F8
TIMERS
6
the time of the read. If the most signicant byte (MSB) ($25 or $27) is read rst, the LSB ($26 or
$28) is transferred to a buffer. This buffer value remains xed after the rst MSB read, even if the
MSB is read several times. This buffer is accessed when the LSB ($26 or $28) is read, and thus,
completes a read sequence of the complete counter value.
6.2.4
Timer B Preset Register
Timer B Preset Register
High byte - $23, Low byte - $24
On the low to high transition of the TMBE bit, the reloadable timer is loaded with the value set in
this 16-bit register.
6.2.5
Timer B Control Status Register
TMBE - Timer B Enable/Disable
1 (set)
Timer B enabled.
0 (clear) –
Timer B disabled.
Upon reset, this bit is cleared and the driving clock of timer B is inhibited, a low to high transition
of this bit loads the timer B counter with the contents of the preset register and activates the driving
clock.
TBOIE - Timer B Time-out Interrupt Enable/Disable
1 (set)
Timer B time-out interrupt enabled.
0 (clear) –
Timer B time-out interrupt disabled.
When this bit is set, timer B time out interrupt will occur if the time out ag (TUF) is set; otherwise,
time out interrupt is disabled.
TCSB1, TCSB0 - Timer B Clock Frequency Select
These two bits are used to select the frequency of timer B driving clock. See Table 6-2.
TUF - Timer B Underow Flag
This bit is set when the counter of Timer B rolls from $0001 to $0000. It should be cleared by
software in the timer B interrupt service routine.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$22
TMBE
TOIE
TCSB1
TCSB0
TUF
00-- -000
TPG
58
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