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| 型號(hào)： | MC68HC05F8B |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 64/126頁(yè) |
| 文件大?。?/td> | 736K |
| 代理商： | MC68HC05F8B |
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MOTOROLA
5-6
MC68HC05F8
INTERRUPTS
5
The interrupt logic recognizes negative edge transitions and pulses (special case of negative
edges) on the external interrupt lines. Figure 5-3 shows both a block diagram and timing for the
interrupt lines (IRQ1, IRQ2) to the processor. The rst method is used if pulses on the interrupt
line are spaced far enough apart to be serviced. The minimum time between pulses is equal to
the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse
occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI
occurs). The second conguration shows several interrupt lines wired-OR to perform the interrupt
at the processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next
interrupt is recognized.
Note:
The internal interrupt latch is cleared in the rst part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during tILIL and serviced
as soon as the I bit is cleared.
5.3.1
External Interrupt Triggering Options (INTN1 & INTN2)
INTN1
1 (set)
–
Negative edge triggering for IRQ1 only.
0 (clear) –
Level and negative edge triggering for IRQ1.
INTN2
1 (set)
–
Negative triggering for IRQ2 only.
0 (clear) –
Level and negative edge triggering for IRQ2.
5.3.2
External Interrupt Enable (INTE1 & INTE2)
INT1E
1 (set)
–
External interrupt IRQ1 enabled.
0 (clear) –
External interrupt IRQ1 disabled.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
System Option Register
$35
TCSA1 TCSA0 INTN1 INTN2
-000 0---
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Event Enable Register
$16
TIMHA INT1E INT2E
000- ----
TPG
40
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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