參數(shù)資料
型號(hào)： MC145170-2
廠商： Motorola, Inc.
英文描述： PLL Frequency Synthesizer With Serial Interface(帶串行口的PLL頻率合成器)
中文描述： 鎖相環(huán)頻率合成器的串行接口（帶串行口的鎖相環(huán)頻率合成器）
文件頁(yè)數(shù)： 16/26頁(yè)
文件大?。?/td> 373K
代理商： MC145170-2
MC145170–2
16
MOTOROLA RF/IF DEVICE DATA
F(s) =
Assuming Gain A Is Very Large, Then:
F(s) =
ζ
=
ω
n =
PHASE–LOCKED LOOP — LOW PASS FILTER DESIGN
(C)
A
C
R2
C
VCO
(A)
φ
R
φ
V
R1
R2
K
φ
KVCO
NR1C
R1sC + 1
ω
n =
ζ
=
ω
nR2C
2
R2sC + 1
R1sC
1. For (C), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from
the midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network
does not significantly affect
ω
n.
2. The
φ
R and
φ
V outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of
the op amp.
3. For the latest information on MC33077 or equivalent, see the Motorola Analog IC web site at http://www.mot–sps.com/analog
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
K
φ
(Phase Detector Gain) = VDD/ 4
π
volts per radian for PDout
K
φ
(Phase Detector Gain) = VDD/2
π
volts per radian for
φ
V and
φ
R
KVCO (VCO Gain) =
2
π
fVCO
VVCO
For a nominal design starting point, the user might consider a damping factor
ζ
≈
0.7 and a natural loop frequency
ω
n
≈
(2
π
fR/50) where
fR is the frequency at the phase detector input. Larger
ω
n values result in faster loop lock times and, for similar sideband filtering, higher
fR–related VCO sidebands.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition).New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley–Interscience, 1980.
Blanchard, Alain, Phase–Locked Loops: Application to Coherent Receiver Design.New York, Wiley–Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley–Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M., Design of Phase–Locked Loop Circuits, with Experiments.Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook.Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook Chapter 17, pp. 538–586. New York, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,” EDN March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1207, The MC145170 in Basic HF and VHF Oscillators, Motorola Semiconductor Products, Inc., 1992.
AN1671, MC145170 PSpice Modeling Kit, Motorola Semiconductor Products, Inc., 1998.
–
+
1
C
VCO
PDout
N
ω
n
2K
φ
KVCO
F(s) =
ζ
=
ω
n =
(B)
(R1+ R2)sC + 1
R2sC + 1
C
VCO
R2
PDout
R1
R1
R1
K
φ
KVCO
NC(R1 + R2)
R2C +
N
K
φ
KVCO
K
φ
KVCO
NCR1
0.5
ω
n
MC33077 or
equivalent
(Note 3)
NOTES:
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MC145170D2R2 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MC145170DT2 功能描述:鎖相環(huán) - PLL PLL Synthesizer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
MC145170DT2R2 功能描述:IC SERIAL PLL FREQ SYNTH 16TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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