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參數(shù)資料
| 型號(hào)： | MC12430FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | MC12430FA |
MC12430
366
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Figure 5. Serial Test Clock Block Diagram
Table 3. DC Characteristics (VCC = 3.3V ±5%)
Symbol
Characteristic
0
°C
25
°C
70
°C
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
2.2
V
VIL
Input LOW Voltage
0.8
V
IIN
Input Current
1.0
mA
VOH
Output HIGH Voltage
TEST
2.5
V
IOH = –0.8mA
VOL
Output LOW Voltage
TEST
0.4
V
IOL = 0.8mA
VOH
Output HIGH Voltage1
FOUT, FOUT
1.
See APPLICATIONS INFORMATION for output level versus frequency information.
2.28
2.60
2.32
2.49
2.38
2.565
V
VCCO = 3.3V
2 3
2.
Output levels will vary 1:1 with VCC0 variation.
3.
50
to V
CC – 2.0V termination.
VOL
Output LOW Voltage1
FOUT, FOUT
1.35
1.67
1.35
1.67
1.35
1.70
V
VCCO = 3.3V
2 3
ICC
Power Supply Current
VCC
PLL_VCC
90
15
110
20
90
15
110
20
90
15
100
20
mA
Table 4. DC Characteristics (VCC = 5.0V ±5%)
Symbol
Characteristic
0
°C
25
°C
70
°C
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
3.5
V
VIL
Input LOW Voltage
0.8
V
IIN
Input Current
1.0
mA
VOH
Output HIGH Voltage
TEST
2.5
V
IOH = –0.8mA
VOL
Output LOW Voltage
TEST
0.4
V
IOL = 0.8mA
VOH
Output HIGH Voltage1
FOUT, FOUT
1.
See APPLICATIONS INFORMATION for output level versus frequency information.
3.98
4.30
4.02
4.19
4.08
4.265
V
VCCO = 5.0V
2 3
2.
Output levels will vary 1:1 with VCC0 variation.
3.
50
to V
CC – 2.0V termination.
VOL
Output LOW Voltage1
FOUT, FOUT
3.05
3.37
3.05
3.37
3.05
3.40
V
VCCO = 5.0V
2 3
ICC
Power Supply Current
VCC
PLL_VCC
90
15
110
20
90
15
110
20
90
15
100
20
mA
FDIV4
MCNT/2
LOW
FOUT
MCNT/2
HIGH
TEST
MUX
7
0
TEST
FOUT
(VIA ENABLE GATE)
N DIVIDE
(1, 2, 4, 8)
0
1
PLL 12430
LATCH
Reset
PLOADB
M COUNTER
SLOAD
T0
T1
T2
VCO
SHIFT
REG
14-BIT
DECODE
SDATA
SCLOCK
MCNT
FREF
SEL_CLK
T2=T1=1, T0=0: Test Mode (PLL bypass)
SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
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