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參數(shù)資料
| 型號(hào)： | MC12430FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MC12430FA |
MC12430
364
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Figure 3. MC12430 Block Diagram (28-Lead PLCC Pinout)
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring the
internal dividers to produce the desired frequency at the
outputs. The output frequency can by represented by this
formula:
FOUT = (FXTAL ÷ 16) x M x 2 ÷ N(1)
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200
≤ M ≤ 400 for any input reference.
Assuming that a 16MHz reference frequency is used the
above equation reduces to:
FOUT = 2 x M
÷ N
Substituting the four values for N (1, 2, 4, 8) yields:
From these ranges the user will establish the value of N
required, then the value of M can be calculated based on the
appropriate equation above. For example if an output frequency
of 131 MHz was desired the following steps would be taken to
identify the appropriate M and N values. 131 MHz falls within
the frequency range set by an N value of 4 so N [1:0] = 01.
For N = 4 FOUT = M
÷ 2 and M = 2 x FOUT. Therefore,
M = 131 x 2 = 262, so M[8:0] = 100000110. Following this same
procedure a user can generate any whole frequency desired
between 50 and 800MHz. Note that for N > 2 fractional values
of FOUT can be realized. The size of the programmable
frequency steps (and thus the indicator of the fractional output
frequencies achievable) will be equal to FXTAL
÷ 8 ÷ N.
For input reference frequencies other than 16MHz, the set of
appropriate equations can be deduced from equation 1. For
computer applications another useful frequency base would be
16.666MHz. From this reference one can generate a family of
output frequencies at multiples of the 33.333MHz PCI clock. As
an example to generate a 133.333MHz clock from a
16.666MHz reference the following M and N values would be
used:
FOUT = 16.666
÷ 16 x M x 2 ÷ N = 1.04166 x M x 2 ÷ N
Let N = 4, M = 133.3333
÷ 1.04166 x 2 = 256
9-BIT SR
2-BIT SR
3-BIT SR
DIV 16
16MHz
S_LOAD
P_LOAD
S_DATA
S_CLOCK
XTAL1
XTAL2
OSC
4
5
PHASE
DETECTOR
28
7
9-BIT DIV M
COUNTER
LATCH
VCO
DIV N
(1, 2, 4, 8)
LATCH
400-800
MHz
FOUT
+3.3 or 5.0V
25
24
23
VCCO
LATCH
TEST
20
+3.3 or 5.0V
PLL_VCC
1MHz
FREF
01
27
26
01
VCC1
+3.3 or 5.0V
M[8:0]
9
8:16
N[1:0]
2
17, 18
21
22, 19
OE
6
FREF_EXT
2
XTAL_SEL
3
DIV 2
200-400
MHz
Table 2. Output Frequency Range
N
FOUT
Output Frequency Range
1
2
4
8
2 x M
M
÷ 2
M
÷ 4
400 – 800 MHz
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
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