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參數(shù)資料
| 型號： | MB91F223SPFV-GSE1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 26/46頁 |
| 文件大小： | 2487K |
| 代理商： | MB91F223SPFV-GSE1 |
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USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
39
Set the maximum data size (Byte) to transmit/receive in one packet
transfer.
Set the value of wMaxPacketSize in request.
When this bit is set to "1", FIFO data register becomes 8-bit mode and
when accessed "FIFO Data Register" of endpoint, lower 8bit[7:0]
becomes effective.
When transmit odd number of byte, it is needed to write in 8-bit mode.
When read in 8-bit mode, set to 8-bit mode before data receive.
When the selected endpoint is set to OUT and if this bit is set to "1",
OUT buffer effective flag and read data (number of byte) is cleared.
In this state(OUT buffer does not become effective state), SIE side
writes data from host into OUT buffer but CPU side does not read.
When set this bit to "1", whatever the transfer direction is, endpoint
buffer (all buffer of single/double buffer) are cleared.
When clear the endpoint buffer, set this bit to "1" and then set again to "0".
To set this bit as "1", Null data addition transmit mode is set .
In the endpoint which is set to continuous transmit mode, when
write a multiple data of maximum packet size into buffer and transmit,
Null data is transmitted automatically after transmitted the last packet.
This setting is effective when continuous transmit mode is set.
Set response PID.
00 : NAK
Whatever the buffer state is, do NAK handshake.
01 : BUF
Response PID is selected according to the state of buffer
and sequence toggle bit. (In bulk/interrupt transfer, one of
ACK, NAK, DATA0, and DATA1)
1x : STALL Do STALL handshake.
If the transfer direction of selected endpoint is OUT, when received
data which exceeded maximum packet size (MXPS), it becomes
"1x" (=STALL) automatically.
Bit
Name
Function
Reset
-
0
W/R
Null data
addition
transmit mode
-
040h
W/R
-
0
W/R
-
0
W/R
-
0
W/R
-
00
W/R
10
EPi_
NULMD
EPi_
ACLR
Set the access mode to endpoint buffer.
0 : CPU access mode
1 : DMA transfer mode
Max Packet size
EPi_
MXPS
[9:0]
FIFO access
8 bit mode
EPi_Octl
OUT buffer
automatic
clear mode
DMA transfer mode
EPi_
DMAMD
Response PID
EPi_
PID
[1:0]
11
12
9 to 0
13
15, 14
W/R
USB
S/W
H/W
NULMD
DMAMD
EPi_MXPS[9:0]
Octl
ACLR
EPi_PID[1:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D15
D13
D14
(4-8) EPi Configuration Register 1 ( i=1 to 5 )
(Address : EP1=62h, EP2=66h, EP3=6Ah, EP4=6Eh, EP5=72h)
The EPi configuration register 1 must be set in a state of response PID is NAK("00").
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