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參數(shù)資料
| 型號： | MB91F223SPFV-GSE1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 2487K |
| 代理商： | MB91F223SPFV-GSE1 |
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USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
32
Af ter "Data1" transmit end
"Data2" write end
"Data3" write start
"Data1" write end
"Data1" write start
In token receive
Before "Data1" transmit end
"Data2" write end
"Data1" transmit end
data1
data transmit impossible
Buff er1
Buff er2
USB side
CPU bus side
Buff er1
Buff er2
writing data
Buff er2
Buff er1
data1
data transmit available
data write available
data2
Buff er2
Buff er1
OUT
transmitting data
writing data
Buff er2
Buff er1
transmitting data
data write completed
IN
data2
Buff er1
Buff er2
data transmit avalable
data write avalable
Buff er1
Buff er2
data transmit avalable
Buff er1
Buff er2
data3
data2
writing data
data
: Data exists in buff er
(2) Transmitting
Below are the transmit status examples
of the endpoint which is set to double buff er.
Endpoint buffer status
Figure 8. Double buff er activ ities-2
"Data1" transmit start
"Data2" write start
data write available
data transmit impossible
OUT
IN
data writeimpossible
data2
data write avalable
Can not transmit because the
transmit buff er is in NotReady.
Request CPU to prepare transmit
data by INTN interrupt
Data write is av ailable during
data transmitting.
When data transmit ended, it occurs
INTR interrupt because the buff er
is in Ready.
End of data write of m aximum packet
size or to set(short packet transmit)
set status, and transmit becomes enable.
And occurs INTR interrupt because
the buff er is in Ready (write enable).
IVAL f lag, it becomes transmit data
End of data write of maximum packet
size or to set (short packet transmit)
set status, and transmit becomes enable.
IVAL flag, it becomes transmit data
When data transmit ended,
because the buff er is in
it occurs INTR interrupt
Ready.
IN
data transmit avalable
IN
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