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參數(shù)資料
| 型號(hào)： | MB91F223SPFV-GSE1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 13/46頁 |
| 文件大?。?/td> | 2487K |
| 代理商： | MB91F223SPFV-GSE1 |
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USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
27
Reset
Function
Name
Bit
Name
Bit
-
1
R
-
0
W/R
-
0
W/R
-
00
W/R
Buffer clear
If "1" is written into this bit When the selected endpoint is set to IN, IN
buffer effective state flag and the data (byte) which is written are cleared.
If IVAL="1" and BCLR="1" is written at the same time, data is cleared
but IN buffer effective state flag is set.(This is effective to transmit 0
length data)
When "1" is written into this bit, if the selected endpoint is set to OUT,
OUT buffer effective state flag is cleared and read data is also cleared.
When "0" is written, this bit is not changed.
If this bit is "0", access to EP0_FIFO data register is enabled.
And when this bit is "0", IVAL and ODLN bit shows the effective value.
EP0_FIFO data register, when read or write, needs cycle time of
200ns (min).
(Continuous access at 5MHz is available)
EP0_FIFO ready
E0req
BCLR
IVAL
EP0_PID
[1:0]
If the control read buffer is selected, this becomes IN buffer
effective state flag.
When set to "1", it becomes to transmit data set state (SIE read enabled).
If data is written which exceeds to the maximum byte of maximum
packet size (MXPS), this bit is set to "1".
When short packet transmit, set this bit to "1" after wrote transmit data.
If the IVAL="1" and BCLR="1" is written at the same time,
IN buffer effective state flag is set.
(This is effective to transmit 0 length data)
If the control readout) buffer is selected, it becomes OUT buffer
effective state status.
Status "1" shows that there is data which can be read.
This bit shows the effective value when E0req bit is "0".
If "1" is written, it is not changed.
If "0" is written, flag is not changed.
In buffer status
Setting the response PID.
00 : NAK Whatever the buffer state is,do NAK handshake.
01 : BUF Response PID is selected by the state of buffer
and sequence toggle bit status.
(One of ACK, NAK, and DATA0/DATA1)
1x : STALL Do STALL handshake
1. When received Setup packet, turns to "00"(=NAK) automatically.
2. When received request (Set_Address, etc.) which is set to
automatic response, turns to "01"(=ACK) automatically after
completed the Setup transaction.
3. If sequence error occurred in control transfer,or received data
in control write transfer which exceed maximum packet size,
this turns to "1x"(=STALL) automatically.
Response PID
11
12
13
15 to 14
W/R
USB
S/W
H/W
CCPL
EP0_PID[1:0]
E0req
BCLR
IVAL
ODLN[7:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D15
D13
D14
(3-9) EP0_FIFO Control Register (Address : 32h)
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