- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69022 > MB91F223SPFV-GSE1 RISC MICROCONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | MB91F223SPFV-GSE1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 22/46頁 |
| 文件大?。?/td> | 2487K |
| 代理商： | MB91F223SPFV-GSE1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
35
-
xxxx
W/R
If the selected endpoint is set to OUT, this becomes to
receive data FIFO register.
If the selected endpoint is set to IN, this becomes to
transmit data FIFO register.
If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] is valid.
When read or write, 200ns (min) of cycle time is needed.
(Continuous access at 5MHz is available)
Read operation when direction IN is appointed or write operation
when direction OUT is appointed, write operation is inhibited.
CPU_FIFO data
CPU_FIFO
[15:0]
15 to 0
Bit
Name
Function
W/R
USB
S/W
H/W
Reset
-
0
W/R
Set the operation mode of DMA transfer.
0 : High speed transfer mode
1 : One word transfer mode
In high speed transfer mode, when endpoint buffer is in read/write enable
in the state that DMA transfer enable, Dreq is asserted.
In one word transfer mode, when endpoint buffer is in read/write enable
in the state that DMA transfer enable and Dack="H", Dreq is asserted.
In both mode, Dreq detects Dack="L" and is negated.
DMA operation
mode
MODE
15
Reset
Function
Name
Bit
Name
Bit
Write/Read "0"
Reserved
14 to 9
-
0
W/R
-
0000
W/R
Write/Read "0"
Appoint the endpoint for DMA transfer.
"0001"=EP1,"0010"=EP2,"0011"=EP3,
"0100"=EP4,"0101"=EP5
EP0 can not be appointed.
Don't change the setting during write (IN) or read (OUT).
Change of the setting of the endpoint of direction IN must
be done after confirmed that IVAL="0" and Dreq="0", or
IVAL="1" and Dreq="1".
Change of the setting of the endpoint of direction OUT must
be done after confirmed that IVAL="0" and Dreq="1".
DMA transfer
endpoint
If this bit is "1", endpoint buffer which is appointed by DMA_EP[3:0]
is enable to write or when read is enable, Dreq is asserted.
If "0" is written in DMA transferring, DMA transfer is forced to end.
DMA transfer
enable
Reserved
DMA_EP
[3:0]
3 to 0
7 to 4
DMAEN
8
W/R
USB
S/W
H/W
MODE
DMAEN
DMA_EP[3:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D15
D13
D14
(4-3) CPU_FIFO Data Register (Address : 44h)
(4-4) DMA_FIFO Selection Register (Address : 48h)
CPU_FIFO[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D15
D13
D14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB91F267APMC | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP64 |
| MB91F267NAPMC | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP64 |
| MB91F361GAPFVS | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP208 |
| MB91F361G | 32-BIT, MROM, 64 MHz, MICROCONTROLLER, PQFP208 |
| MB91F368GA | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP120 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91F233 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F233APFF-GE1 | 制造商:FUJITSU 功能描述:IC 32BIT MCU 5V SMD LQFP120 |
| MB91F233L | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F233LLGA-GE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F233LPFF-GE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。