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參數(shù)資料
| 型號： | MB91F158PMC1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 14 X 14 MM, 1.70 MM HEIGHT, 0.40 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 22/92頁 |
| 文件大?。?/td> | 2193K |
| 代理商： | MB91F158PMC1 |
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MB91F158 Series
DS07-16316-2E
29
■ PERIPHERAL RESOURCES
1.
I/O Port
(1) Port Block Diagram
This LSI is available as an I/O port when the resource associated with each pin is set not to use a pin for input/
output.
The pin level is read from the port (PDR) when it is set for input. When the port is set for output, the value in the
data register is read. The same also applies to reload by read modify write.
When switching from input to output, output data is set in the data register beforehand. However, if a read modify
write instruction (such as bit set) is used at that time, keep in mind that it is the input data from the pin that is
read, not the latch value of the data register.
Basic I/O Port
Figure PORT-1 Basic port block
The I/O port consists of the PDR (Port Data Register) and the DDR (Data Direction Register) .
Note :
AIC controls switching between the resource and port of the analog pin (A/D) .
AICK (Analog Input Control register on port-K)
The register controls whether port K should be used for analog input or as a general-purpose port.
0 : General-purpose port
1 : Analog input (A/D)
In input mode (DDR
= “0”) → PDR read : Reads the level of the corresponding external pin.
PDR write : Writes the set value to the PDR.
In output mode (DDR
= “1”) → PDR read : Reads the PDR value.
PDR write : Outputs the PDR value to the corresponding external pin.
Data bus
PDR read
0
1
0
1
Pin
PDR
DDR
PDR : Port Data Register
DDR : Data Direction Register
Resource input
Resource output
allowed
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