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參數(shù)資料
| 型號： | MB90V520 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 9/106頁 |
| 文件大?。?/td> | 1539K |
| 代理商： | MB90V520 |
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MB90520 Series
9
Pin no.
LQFP-120*
1
QFP-120*
2
117
Pin name
Circuit
type
Function
P26
ZIN0
E
This is a general-purpose I/O port.
This port can be used as count clock Z input for 8/16-bit up/down
counter/timer 0.
This is a request input pin of the DTP/external interrupt circuit
ch.7.
This is a general-purpose I/O port.
This is an external trigger input pin of the 8/10-bit A/D converter.
Since this input is used as required for 8/10-bit A/D converter input
operation, output by other functions must be suspended except for
intentional operation.
This is a general-purpose I/O port.
This is a general-purpose I/O port.
This is a clock monitor function output pin.
This function is valid when clock monitor output is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT0 is disabled.
This is an event output pin for output compare 0 (OCU) ch.0.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT1 is disabled.
This is an event output pin for output compare 0 (OCU) ch.1.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT2 is disabled.
This is an event output pin for output compare 0 (OCU) ch.2.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the
OUT3 is disabled.
This is an event output pin for output compare 0 (OCU) ch.3.
This function is valid when output for each channel is enabled.
This is a general-purpose I/O port.
This function becomes valid when waveform output from the PG00
is disabled.
This is an output pin of 8/16-bit PPG timer 0.
This function becomes valid when waveform output from PG00 is
enabled.
INT7
118
P27
ADTG
E
120
1
P30
P31
CKOT
E
E
2
P32
E
OUT0
3
P33
E
OUT1
4
P34
E
OUT2
5
P35
E
OUT3
6
P36
E
PG00
(Continued)
*1: FPT-120P-M05
*2: FPT-120P-M13
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| MB90523 | Quadruple 2-Input Positive-NAND Gates 20-LCCC -55 to 125 |
| MB90523PFF | 16-bit Proprietary Microcontroller |
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