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參數(shù)資料
| 型號(hào)： | MB90V520 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 61/106頁(yè) |
| 文件大小： | 1539K |
| 代理商： | MB90V520 |
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MB90520 Series
61
10. DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the
F
2
MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit*
for transmission to the F
2
MC-16LX CPU. It is used to activate the intelligent I/O service or interrupt processing.
As with request levels, two types of “H” and “L” can be selected for the intelligent I/O service. Rising and falling
edges as well as “H” and “L” can be selected for an external interrupt request.
* :The external peripheral circuit is connected outside the MB90520 series device.
(1) Register Configuration
DTP/interrupt factor register (EIRR)
Address
000031
H
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Initial value
XXXXXXXX
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
000030
H
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000
B
Address
ELVR (lower) : 000032
H
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000
B
DTP/interrupt enable register (ENIR)
R/W: Readable and writable
X : Indeterminate
Address
ELVR (upper) : 000033
H
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
Initial value
00000000
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Request level setting register (ELVR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
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