參數(shù)資料
型號(hào)： MB90V520
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller
中文描述： 16位微控制器專有
文件頁(yè)數(shù)： 77/106頁(yè)
文件大?。?/td> 1539K
代理商： MB90V520
MB90520 Series
77
20. Low-power Consumption (Stand-by) Mode
The F
2
MC-16LX has the following CPU operating modes configured by selection of an operating clock and clock
operation control.
Clock mode
PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation
clock.
Main clock mode: A mode in which the CPU and peripheral equipment are driven by drivided-by-2 of the
oscillation clock. The PLL multiplication circuits stops in the main clock mode.
Sub-clock mode
The sub-clock mode causes the CPU to operate only with the sub-clock. This mode uses the sub-clock
frequency divided by four as the operating clock frequency while stopping the main clock and PLL clock.
CPU intermittent operation mode
The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU
intermittently while external bus and peripheral functions are operated at a high speed.
Hardware stand-by mode
The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU
by the low-power consumption control circuit (sleep mode), stopping clock supplies to the CPU and peripheral
functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware stand-by mode). Of
these modes, modes other than the PLL clock mode are low power consumption modes.
(1) Register Configuration
Clock select register (CKSCR)
Address
0000A1
H
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Address
0000A0
H
STP
SLP
SPL
RST
TMD
CG1
CG0
SSR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W
W
R/W
W
W
R/W
R/W
R/W
R/W: Readable and writable
R : Read only
W : Write only
Low-power consumption mode control register (LPMCR)
Initial value
00011000
B
Initial value
11111100
B
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