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參數(shù)資料
| 型號(hào)： | MB90V520 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 32/106頁 |
| 文件大?。?/td> | 1539K |
| 代理商： | MB90V520 |
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MB90520 Series
32
I
PERIPHERALS
1. I/O Port
(1) Input/Output Port
Port 0 through A are general-purpose I/O ports having a combined function as a resource input. The I/O ports
can be used as general-purpose I/O ports only in the single-chip mode.
Operation as output port
The pin is configured as an output port by setting the corresponding bit of the DDR register to “1”.
Writing data to PDR register when the port is configured as output, the data is retained in the output latch in
the PDR and directly output to the pin.
The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR
register.
Note: When a read-modify-write type instruction (e.g. bit set instruction) is performed to the port data register,
the destination bit of the operation is set to the specified value, not affecting the bits configured by the
DDR register for output. However, values of bits configured as inputs by the DDR register are changed
because input values to the pins are written into the output latch. To avoid this situation, configure the
pins by the DDR register as output after writing output data to the PDR register when switching the bit
used as input to output.
Operation as input port
The pin is configured as input by setting the corresponding bit of the DDR register to “0.”
When the pin is configured as an input, the output buffer is turned off and the pin is put into a high-impedance
status.
When data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs
are unaffected.
Reading the PDR register reads out the pin level (“0” or “1”).
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