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參數(shù)資料
| 型號： | MB90V520 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 29/106頁 |
| 文件大小： | 1539K |
| 代理商： | MB90V520 |
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MB90520 Series
29
(Continued)
Descriptions for read/write
R/W: Readable and writable
R: Read only
W: Write only
Descriptions for initial value
0 : The initial value is “0.”
1 : The initial value is “1.”
X : The initial value is indeterminate.
*1: This area is the only external access area having an address of 0000FF
H
or lower. An access operation to this
area is handled as that to external I/O area.
*2: For details of the “RAM area”, see the memory map.
*3: The “reserved area” is basically disabled because it is used in the system.
*4: “Area used by the system” is the area set by the resistor for evaluating tool.
Notes: For bits initialized by reset operations, the initial value set by the reset operation is listed as an initial value.
Note that the values are different from reading results.
For LPMCR/CKSCR/WDTC, there are cases in which initialization is performed or not performed,
depending on the types of the reset. The value listed is the initial value in cases where initialization is per
formed.
The addresses following 0000FF
H
are reserved. No external bus access signal is generated.
Boundary ####
H
between the “RAM area” and the“ reserved area” varies with the product models.
Channels 0 to 3 of the OCU compare register use 16-bit free-run timer 2, while channels 4 to 7 of the OCU
compare register use 16-bit free-run timer 1. 16-bit free-run timer 1 is also used by input captures (ICU)
0 and 1.
Address
Abbreviated
register
name
ICR14
ICR15
Register name
Read/
write
Resource name
Initial value
0000BE
H
0000BF
H
0000C0
H
to
0000FF
H
000100
H
to
00####
H
00####
H
to
001FEF
H
001FF0
H
001FF1
H
001FF2
H
001FF3
H
001FF4
H
001FF5
H
001FF6
H
to
001FFF
H
Interrupt control register 14
Interrupt control register 15
R/W
R/W
Interrupt
controller
0 0 0 0 0 1 1 1
B
0 0 0 0 0 1 1 1
B
(External area)*
1
(RAM area)*
2
(Reserved area)*
3
PADR0
Program address detection register 0
Program address detection register 1
Program address detection register 2
Program address detection register 3
Program address detection register 4
Program address detection register 5
R/W
R/W
R/W
R/W
R/W
R/W
Address match
detection
function
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
PADR1
(Reserved area)*
3
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